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公开(公告)号:US20210111862A1
公开(公告)日:2021-04-15
申请号:US17132058
申请日:2020-12-23
申请人: Vikram Dadwal , James Coleman , Alexander Slota
发明人: Vikram Dadwal , James Coleman , Alexander Slota
摘要: Systems and techniques for an heterogeneous clock management solution for industrial systems are described herein. In an example, a system includes a clock management circuit adapted to receive core timing information from a core of an integrated circuit. The clock management circuit is further adapted to correlate the core timing information with a reference clock. The clock management circuit is further adapted to output frequency and time offset of the reference clock to the core timing information. The system includes an execution circuit adapted to schedule a transaction from the core at a scheduled time relative to the reference clock using the frequency and time offset. The execution circuit is further adapted to issue a command to execute the transaction at the scheduled time.
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公开(公告)号:US20190138462A1
公开(公告)日:2019-05-09
申请号:US16236057
申请日:2018-12-28
IPC分类号: G06F13/12 , G06F12/1081 , G06F13/28
CPC分类号: G06F13/128 , G06F12/1081 , G06F13/28 , G06F2213/2802 , G06F2213/2806
摘要: System and techniques for enhanced electronic navigation maps for a vehicle are described herein. A descriptor set-up message may be received at a network controller interface (NIC). Here, the descriptor set-up message includes an ethernet frame descriptor. The NIC may then use the ethernet frame descriptor to transmit, across a physical interface of the NIC, multiple ethernet frames, each of which use the same ethernet frame descriptor from the set-up message.
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