公开(公告)号：US07844927B2

公开(公告)日：2010-11-30

申请号：US11655534

申请日：2007-01-19

Applicant: Zhi-Yuan Wu ,  Ali Icel ,  Judy X. An ,  Ciby T. Thuruthiyil

Inventor： Zhi-Yuan Wu ,  Ali Icel ,  Judy X. An ,  Ciby T. Thuruthiyil

IPC: G06F17/50

CPC classification number: G06F17/5036

Abstract: According to one exemplary embodiment, a method for producing a quality assured semiconductor device model when at least one critical parameter of a semiconductor device process is upgraded includes verifying the quality assured semiconductor device model for consistency against measured data or projected targets. The method further includes verifying the quality assured semiconductor device model for accuracy and consistency when one of a number of critical parameters is varied. The method further includes verifying consistency of the quality assured semiconductor device model against an old semiconductor device model. The method further includes verifying the quality assured semiconductor device model over a range of each of a number of semiconductor device dependencies. The method further includes verifying the quality assured semiconductor device model for digital circuit operation. The method further includes verifying the quality assured semiconductor device model for analog circuit operation. The method further includes verifying convergence of the quality assured semiconductor device model.

Abstract translation: 根据一个示例性实施例，当升级半导体器件工艺的至少一个关键参数时，用于产生质量有保证的半导体器件模型的方法包括：验证半导体器件的质量保证模型与测量数据或预测目标的一致性。 该方法还包括当多个关键参数之一变化时，验证半导体器件的质量保证模型的准确性和一致性。 该方法还包括验证保证质量的半导体器件模型与旧的半导体器件模型的一致性。 该方法还包括在多个半导体器件依赖性中的每一个的范围内验证保证质量的半导体器件模型。 该方法还包括验证用于数字电路操作的质量保证的半导体器件模型。 该方法还包括验证用于模拟电路操作的质量保证的半导体器件模型。 该方法还包括验证质量保证的半导体器件模型的收敛。

公开(公告)号：US20090184372A1

公开(公告)日：2009-07-23

申请号：US12413185

申请日：2009-03-27

Applicant: Ali ICEL ,  Qiang CHEN ,  Mario M. PELELLA

Inventor： Ali ICEL ,  Qiang CHEN ,  Mario M. PELELLA

IPC: H01L29/78

CPC classification number: H01L27/1203 ,  H01L21/823437 ,  H01L21/823481 ,  H01L21/84

Abstract: SOI semiconductor components and methods for their fabrication are provided wherein the SOI semiconductor components include an MOS transistor in the supporting semiconductor substrate. In accordance with one embodiment the component comprises a semiconductor on insulator (SOI) substrate having a first semiconductor layer, a layer of insulator on the first semiconductor layer, and a second semiconductor layer overlying the layer of insulator. The component includes source and drain regions of a first conductivity type and first doping concentration in the first semiconductor layer. A channel region of a second conductivity type is defined between the source and drain regions. A gate insulator and gate electrode overlie the channel region. A drift region of the first conductivity type is located between the channel region and the drain region, the drift region having a second doping concentration less than the first doping concentration of the first conductivity determining dopant.

Abstract translation: 提供SOI半导体元件及其制造方法，其中SOI半导体元件包括支撑半导体衬底中的MOS晶体管。 根据一个实施例，该部件包括具有第一半导体层，第一半导体层上的绝缘体层和覆盖绝缘体层的第二半导体层的绝缘体上半导体衬底（SOI）衬底。 该部件包括第一导电类型的源区和漏区以及第一半导体层中的第一掺杂浓度。 在源区和漏区之间限定第二导电类型的沟道区。 栅极绝缘体和栅极电极覆盖沟道区域。 第一导电类型的漂移区域位于沟道区域和漏极区域之间，漂移区域具有小于第一导电性确定掺杂剂的第一掺杂浓度的第二掺杂浓度。

公开(公告)号：US20080177523A1

公开(公告)日：2008-07-24

申请号：US11655534

申请日：2007-01-19

Applicant: Zhi-Yuan Wu ,  Ali Icel ,  Judy X. An ,  Ciby T. Thuruthiyil

Inventor： Zhi-Yuan Wu ,  Ali Icel ,  Judy X. An ,  Ciby T. Thuruthiyil

IPC: G06F17/50

CPC classification number: G06F17/5036

Abstract: According to one exemplary embodiment, a method for producing a quality assured semiconductor device model when at least one critical parameter of a semiconductor device process is upgraded includes verifying the quality assured semiconductor device model for consistency against measured data or projected targets. The method further includes verifying the quality assured semiconductor device model for accuracy and consistency when one of a number of critical parameters is varied. The method further includes verifying consistency of the quality assured semiconductor device model against an old semiconductor device model. The method further includes verifying the quality assured semiconductor device model over a range of each of a number of semiconductor device dependencies. The method further includes verifying the quality assured semiconductor device model for digital circuit operation. The method further includes verifying the quality assured semiconductor device model for analog circuit operation. The method further includes verifying convergence of the quality assured semiconductor device model.

Abstract translation: 根据一个示例性实施例，当升级半导体器件工艺的至少一个关键参数时，用于产生质量有保证的半导体器件模型的方法包括：验证半导体器件的质量保证模型与测量数据或预测目标的一致性。 该方法还包括当多个关键参数之一变化时，验证半导体器件的质量保证模型的准确性和一致性。 该方法还包括验证保证质量的半导体器件模型与旧的半导体器件模型的一致性。 该方法还包括在多个半导体器件依赖性中的每一个的范围内验证保证质量的半导体器件模型。 该方法还包括验证用于数字电路操作的质量保证的半导体器件模型。 该方法还包括验证用于模拟电路操作的质量保证的半导体器件模型。 该方法还包括验证质量保证的半导体器件模型的收敛。

公开(公告)号：US07986008B2

公开(公告)日：2011-07-26

申请号：US12413185

申请日：2009-03-27

Applicant: Ali Icel ,  Qiang Chen ,  Mario M. Pelella

Inventor： Ali Icel ,  Qiang Chen ,  Mario M. Pelella

IPC: H01L27/12

CPC classification number: H01L27/1203 ,  H01L21/823437 ,  H01L21/823481 ,  H01L21/84

Abstract: SOI semiconductor components and methods for their fabrication are provided wherein the SOI semiconductor components include an MOS transistor in the supporting semiconductor substrate. In accordance with one embodiment the component comprises a semiconductor on insulator (SOI) substrate having a first semiconductor layer, a layer of insulator on the first semiconductor layer, and a second semiconductor layer overlying the layer of insulator. The component includes source and drain regions of a first conductivity type and first doping concentration in the first semiconductor layer. A channel region of a second conductivity type is defined between the source and drain regions. A gate insulator and gate electrode overlie the channel region. A drift region of the first conductivity type is located between the channel region and the drain region, the drift region having a second doping concentration less than the first doping concentration of the first conductivity determining dopant.

Abstract translation: 提供SOI半导体元件及其制造方法，其中SOI半导体元件包括支撑半导体衬底中的MOS晶体管。 根据一个实施例，该部件包括具有第一半导体层，第一半导体层上的绝缘体层和覆盖绝缘体层的第二半导体层的绝缘体上半导体衬底（SOI）衬底。 该部件包括第一导电类型的源区和漏区以及第一半导体层中的第一掺杂浓度。 在源区和漏区之间限定第二导电类型的沟道区。 栅极绝缘体和栅极电极覆盖沟道区域。 第一导电类型的漂移区域位于沟道区域和漏极区域之间，漂移区域具有小于第一导电性确定掺杂剂的第一掺杂浓度的第二掺杂浓度。

公开(公告)号：US07531403B2

公开(公告)日：2009-05-12

申请号：US11538001

申请日：2006-10-02

Applicant: Ali Icel ,  Qiang Chen ,  Mario M. Pelella

Inventor： Ali Icel ,  Qiang Chen ,  Mario M. Pelella

IPC: H01L21/8238

CPC classification number: H01L27/1203 ,  H01L21/823437 ,  H01L21/823481 ,  H01L21/84

Abstract: SOI semiconductor components and methods for their fabrication are provided wherein the SOI semiconductor components include an MOS transistor in the supporting semiconductor substrate. In accordance with one embodiment the component comprises a semiconductor on insulator (SOI) substrate having a first semiconductor layer, a layer of insulator on the first semiconductor layer, and a second semiconductor layer overlying the layer of insulator. The component includes source and drain regions of first conductivity type and first doping concentration in the first semiconductor layer. A channel region of second conductivity type is defined between the source and drain regions. A gate insulator and gate electrode overlie the channel region. A drift region of first conductivity type is located between the channel region and the drain region, the drift region having a second doping concentration less than the first doping concentration of first conductivity determining dopant.

Abstract translation: 提供SOI半导体元件及其制造方法，其中SOI半导体元件包括支撑半导体衬底中的MOS晶体管。 根据一个实施例，该部件包括具有第一半导体层，第一半导体层上的绝缘体层和覆盖绝缘体层的第二半导体层的绝缘体上半导体衬底（SOI）衬底。 该部件包括第一半导体层中的第一导电类型和第一掺杂浓度的源区和漏区。 在源区和漏区之间限定第二导电类型的沟道区。 栅极绝缘体和栅极电极覆盖沟道区域。 第一导电类型的漂移区域位于沟道区域和漏极区域之间，漂移区域具有小于第一导电性确定掺杂剂的第一掺杂浓度的第二掺杂浓度。

公开(公告)号：US20080079074A1

公开(公告)日：2008-04-03

申请号：US11538001

申请日：2006-10-02

Applicant: Ali Icel ,  Qiang Chen ,  Mario M. Pelella

Inventor： Ali Icel ,  Qiang Chen ,  Mario M. Pelella

IPC: H01L27/12

CPC classification number: H01L27/1203 ,  H01L21/823437 ,  H01L21/823481 ,  H01L21/84

Abstract: SOI semiconductor components and methods for their fabrication are provided wherein the SOI semiconductor components include an MOS transistor in the supporting semiconductor substrate. In accordance with one embodiment the component comprises a semiconductor on insulator (SOI) substrate having a first semiconductor layer, a layer of insulator on the first semiconductor layer, and a second semiconductor layer overlying the layer of insulator. The component includes source and drain regions of first conductivity type and first doping concentration in the first semiconductor layer. A channel region of second conductivity type is defined between the source and drain regions. A gate insulator and gate electrode overlie the channel region. A drift region of first conductivity type is located between the channel region and the drain region, the drift region having a second doping concentration less than the first doping concentration of first conductivity determining dopant.

Abstract translation: 提供SOI半导体元件及其制造方法，其中SOI半导体元件包括支撑半导体衬底中的MOS晶体管。 根据一个实施例，该部件包括具有第一半导体层，第一半导体层上的绝缘体层和覆盖绝缘体层的第二半导体层的绝缘体上半导体衬底（SOI）衬底。 该部件包括第一半导体层中的第一导电类型和第一掺杂浓度的源区和漏区。 在源区和漏区之间限定第二导电类型的沟道区。 栅极绝缘体和栅极电极覆盖沟道区域。 第一导电类型的漂移区域位于沟道区域和漏极区域之间，漂移区域具有小于第一导电性确定掺杂剂的第一掺杂浓度的第二掺杂浓度。