公开(公告)号：US06367051B1

公开(公告)日：2002-04-02

申请号：US09096810

申请日：1998-06-12

Applicant: Lawrence Pileggi ,  Sharad Malik ,  Emre Tuncer ,  Abhijeet Chakraborty ,  Satyamurthy Pullela ,  Altan Odabasioglu ,  Douglas B. Boyle

Inventor： Lawrence Pileggi ,  Sharad Malik ,  Emre Tuncer ,  Abhijeet Chakraborty ,  Satyamurthy Pullela ,  Altan Odabasioglu ,  Douglas B. Boyle

IPC: G06F1750

CPC classification number: G06F17/505

Abstract: A design tool for integrated circuits includes a placement tool which concurrently places logic gates and interconnect. In one embodiment, the logic gates are placed into bins and virtual buffers are inserted between logic gates mapped to different bins. Placement and interconnect wire lengths and densities are successively improved leading to removal of some buffers and actualization of the virtual buffers.

Abstract translation: 用于集成电路的设计工具包括同时放置逻辑门和互连的放置工具。 在一个实施例中，逻辑门被放置到存储区中，并且虚拟缓冲器被插入映射到不同仓的逻辑门之间。 放置和互连线长度和密度被连续改善，导致一些缓冲器的移除和虚拟缓冲器的实现。