公开(公告)号：US20230315467A1

公开(公告)日：2023-10-05

申请号：US17712103

申请日：2022-04-02

申请人： Eliyah Kilada ,  Ammon Christiansen ,  Ariel Fabien Sabba ,  Christopher Celio ,  Ankur Groen ,  Muhammad Faisal Azeem ,  Malihe Ahmadi ,  Rangeen Basu Roy Chowdhury

发明人： Eliyah Kilada ,  Ammon Christiansen ,  Ariel Fabien Sabba ,  Christopher Celio ,  Ankur Groen ,  Muhammad Faisal Azeem ,  Malihe Ahmadi ,  Rangeen Basu Roy Chowdhury

IPC分类号： G06F9/38 ,  G06F9/30 ,  G06F12/0811

CPC分类号： G06F9/3802 ,  G06F9/3867 ,  G06F12/0811 ,  G06F9/30043 ,  G06F9/30047

摘要： First and second instruction storage are coupled with a fetch unit including sets of fetch circuitry each spanning a plurality of pipeline stages. A first set of fetch circuitry is to initiates a fetch operation for a block of instructions, and has an indication to read the block of instructions from the second instruction storage. The first set retains the fetch operation for the block of instructions at a pipeline stage of the plurality, for one or more cycles, until a hazard corresponding to the pipeline stage of the first set of fetch circuitry has been removed. The first set stores the block of instructions from the second instruction storage to the first instruction storage, during the one or more cycles. The first set reads the block of instructions from the first instruction storage, for the fetch operation, once the hazard has been removed.

公开(公告)号：US20230315466A1

公开(公告)日：2023-10-05

申请号：US17712101

申请日：2022-04-02

申请人： Eliyah Kilada ,  Ammon Christiansen ,  Ariel Fabien Sabba ,  Christopher Celio ,  Ankur Groen ,  Muhammad Faisal Azeem ,  Malihe Ahmadi ,  Rangeen Basu Roy Chowdhury

发明人： Eliyah Kilada ,  Ammon Christiansen ,  Ariel Fabien Sabba ,  Christopher Celio ,  Ankur Groen ,  Muhammad Faisal Azeem ,  Malihe Ahmadi ,  Rangeen Basu Roy Chowdhury

IPC分类号： G06F9/38 ,  G06F9/30

CPC分类号： G06F9/3802 ,  G06F9/3867 ,  G06F9/3861 ,  G06F9/30047

摘要： At least one instruction storage coupled with a fetch unit including sets of fetch circuitry each having a same plurality of pipeline stages. The sets of fetch circuitry perform fetch operations to fetch blocks of instructions from the at least one instruction storage. Stall circuitry, in response to an indication of a hazard for a given pipeline stage of a first set of fetch circuitry, retains a fetch operation for a first block of instructions at the given pipeline stage, and zero or more fetch operations for zero or more corresponding blocks of instructions at zero or more preceding pipeline stages of the first set of fetch circuitry, until the hazard has been removed. The stall circuitry advances a fetch operation for a second block of instructions from the given pipeline stage of a second set of fetch circuitry, during an initial cycle of the one or more cycles.