公开(公告)号：US07010672B2

公开(公告)日：2006-03-07

申请号：US10317875

申请日：2002-12-11

申请人： Sagheer Ahmad ,  Anand Shirwal

发明人： Sagheer Ahmad ,  Anand Shirwal

IPC分类号： G06F9/44 ,  G06F11/36

CPC分类号： G06F11/3648

摘要： A digital processor having a programmable breakpoint/watchpoint (BWP) trigger circuit that generates BWP triggers in response to user-defined combinations and/or sequences of trigger events. Several trigger event detection registers generate pre-trigger signals when stored trigger values (e.g., instruction addresses or data addresses/values) match addresses/values transmitted on busses within the processor core. Sum-of-products circuits generate intermediate combinational trigger signals in accordance with user-defined combinations of the pre-trigger signals. A finite state machine generates an intermediate sequential trigger signal in response to user-defined sequences of the intermediate combinational trigger signals. Either the intermediate combinational trigger signals or the intermediate sequential trigger signal are selectively passed to an action generator, which transmits an associated breakpoint or watchpoint trigger signal to a decode stage of the processor core or other destination.

摘要翻译： 具有可编程断点/观察点（BWP）触发电路的数字处理器，其根据用户定义的组合和/或触发事件序列产生BWP触发。 当存储的触发值（例如，指令地址或数据地址/值）匹配在处理器核心内的总线上发送的地址/值时，若干触发事件检测寄存器产生预触发信号。 产品总和电路根据用户定义的预触发信号的组合产生中间组合触发信号。 有限状态机响应于中间组合触发信号的用户定义的序列产生中间顺序触发信号。 中间组合触发信号或中间顺序触发信号被选择性地传递到动作发生器，动作发生器将关联的断点或观察点触发信号发送到处理器核心或其他目的地的解码级。