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公开(公告)号：US20070288735A1
公开(公告)日：2007-12-13
申请号：US11449858
申请日：2006-06-09
IPC分类号： G06F9/00
CPC分类号： G06F9/3851 , G06F9/30101 , G06F9/3848
摘要： A branch prediction mechanism 16, 18 within a multithreaded processor having hardware scheduling logic 6, 8, 10, 12 uses a shared global history table 18 which is indexed by respective branch history registers 20, 22 for each program thread. Different mappings are used between preceding branch behaviour and the prediction value stored within respective branch history registers 20, 22. These different mappings may be provided by inverters placed into the shift in paths for the branch history registers 20, 22 or by adders 40, 42 or in some other way. The different mappings help to equalise the probability of use of the particular storage locations within the global history table 18 such that the plurality of program threads are not competing excessively for the same storage locations corresponding to the more commonly occurring patterns of preceding branch behaviour.
摘要翻译： 具有硬件调度逻辑6,8,10,12的多线程处理器内的分支预测机制16,18使用共享全局历史表18，该共享全局历史表18由各个分支历史寄存器20,22针对每个程序线索引。 在之前的分支行为与存储在相应分支历史寄存器20,22内的预测值之间使用不同的映射。 这些不同的映射可以由放置在用于分支历史寄存器20,22的路径中的变换器或由加法器40,42或以某种其他方式提供。 不同的映射有助于使全局历史表18中的特定存储位置的使用概率相等，使得多个程序线程对于与先前分支行为的更常见的模式相对应的相同存储位置不会过度竞争。
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公开(公告)号：US20070226473A1
公开(公告)日：2007-09-27
申请号：US11592323
申请日：2006-11-03
申请人： Andrei Kapustin , Yuri Ledvik , Vladimir Vasekin
发明人： Andrei Kapustin , Yuri Ledvik , Vladimir Vasekin
IPC分类号： G06F9/44
CPC分类号： G06F11/3648
摘要： A data processing system 2 is provided with breakpoint circuitry 28 having breakpoint registers 30 which can specify a variety of different types of breakpoint conditions. These breakpoint conditions include register access breakpoints which are triggered when an access is made to either a general purpose register 8 or a configuration register 22, 24. The breakpoints can also include input/output port access breakpoints which are triggered when an access is made to a predetermined one of a plurality of input/output ports 26 by an appropriate program instruction or in another way.
摘要翻译： 数据处理系统2具有断点电路28，断点电路28具有可指定各种不同类型的断点条件的断点寄存器30。 这些断点条件包括当访问通用寄存器8或配置寄存器22,24时被触发的寄存器访问断点。 断点还可以包括当通过适当的程序指令或以另一种方式对多个输入/输出端口26中的预定的一个进行访问时触发的输入/输出端口访问断点。
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公开(公告)号：US07877587B2
公开(公告)日：2011-01-25
申请号：US11449858
申请日：2006-06-09
CPC分类号： G06F9/3851 , G06F9/30101 , G06F9/3848
摘要： A branch prediction mechanism 16, 18 within a multithreaded processor having hardware scheduling logic 6, 8, 10, 12 uses a shared global history table 18 which is indexed by respective branch history registers 20, 22 for each program thread. Different mappings are used between preceding branch behavior and the prediction value stored within respective branch history registers 20, 22. These different mappings may be provided by inverters placed into the shift in paths for the branch history registers 20, 22 or by adders 40, 42 or in some other way. The different mappings help to equalise the probability of use of the particular storage locations within the global history table 18 such that the plurality of program threads are not competing excessively for the same storage locations corresponding to the more commonly occurring patterns of preceding branch behavior.
摘要翻译： 具有硬件调度逻辑6,8,10,12的多线程处理器内的分支预测机制16,18使用共享全局历史表18，该共享全局历史表18由各个分支历史寄存器20,22针对每个程序线索引。 在先前的分支行为和存储在相应的分支历史寄存器20,22中的预测值之间使用不同的映射。这些不同的映射可以由放置在分支历史寄存器20,22的路径中的反相器或由加法器40,42 或以其他方式。 不同的映射有助于使全局历史表18中的特定存储位置的使用概率相等，使得多个程序线程对于与先前分支行为的更常见的模式相对应的相同存储位置不会过度竞争。
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公开(公告)号：US08010774B2
公开(公告)日：2011-08-30
申请号：US11592323
申请日：2006-11-03
申请人： Andrei Kapustin , Yuri Ledvik , Vladimir Vasekin
发明人： Andrei Kapustin , Yuri Ledvik , Vladimir Vasekin
IPC分类号： G06F15/177
CPC分类号： G06F11/3648
摘要： A data processing system is provided with breakpoint circuitry having breakpoint registers which can specify a variety of different types of breakpoint conditions. These breakpoint conditions include register access breakpoints which are triggered when an access is made to either a general purpose register or a configuration register. The breakpoints can also include input/output port access breakpoints which are triggered when an access is made to a predetermined one of a plurality of input/output ports by an appropriate program instruction or in another way.
摘要翻译： 数据处理系统具有断点电路，断点电路具有可指定各种不同类型的断点条件的断点寄存器。 这些断点条件包括当访问通用寄存器或配置寄存器时触发的寄存器访问断点。 断点还可以包括当通过适当的程序指令或以另一种方式对多个输入/输出端口中的预定的一个进行访问时触发的输入/输出端口访问断点。
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公开(公告)号：US20070226471A1
公开(公告)日：2007-09-27
申请号：US11373514
申请日：2006-03-13
申请人： Andrei Kapustin , Yuri Levdik , Vladimir Vasekin
发明人： Andrei Kapustin , Yuri Levdik , Vladimir Vasekin
IPC分类号： G06F9/44
CPC分类号： G06F11/3648
摘要： A data processing apparatus, method and watch point unit are disclosed. The data processing apparatus comprises: a processor core operable to process a sequence of instructions; and a watch point unit operable to receive an indication of each of the sequence of instructions being processed by the processor core, the watch point unit being operable to determine whether the indication of each of the sequence of instructions correlates with at least one watch point condition and, if so, the watch point unit being further operable to provide an indication that the at least one watch point condition occurred. Accordingly, watch point conditions can be set based on the instructions themselves rather than being based on a likely effect of that instruction. This enables a wider range of conditions of interest to be defined which expands the usefulness of debugging. Also, the determination of when the conditions of interest occur can be more precisely made, which significantly reduces the effort required when analyzing events which may or may not have caused an unexpected operation to occur.
摘要翻译： 公开了一种数据处理装置，方法和观察点单元。 数据处理装置包括：处理器核，可操作以处理指令序列; 以及观察点单元，其可操作以接收由处理器核心正在处理的每个指令序列的指示，观察点单元可操作以确定指令序列中的每一个的指示是否与至少一个观察点条件相关 如果是，则观察点单元进一步可操作以提供发生所述至少一个观察点状况的指示。 因此，可以基于指令本身来设置观察点条件，而不是基于该指令的可能的效果。 这使得能够定义更广泛的感兴趣的条件，这扩大了调试的有用性。 此外，可以更准确地确定何时出现的情况，当分析可能引起或可能未引起意外操作发生的事件时，这显着地减少了所需的努力。
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