公开(公告)号：US07155054B2

公开(公告)日：2006-12-26

申请号：US11022165

申请日：2004-12-23

申请人： Arun Rao

发明人： Arun Rao

IPC分类号： G06K9/00 ,  G06F15/00 ,  G06F13/00

CPC分类号： G06T11/001

摘要： A system for efficiently converting computer graphics images to film images with accurate color management is described. The system involves the creation of a direct mapping of chromaticity and intensity data from the values used to generate images on a computer monitor to the values used to display the images on projected motion picture film.

摘要翻译： 描述了一种用于将计算机图形图像有效地转换成具有精确颜色管理的胶片图像的系统。 该系统包括从用于在计算机监视器上生成图像的值的色度和强度数据的直接映射到用于在投影电影胶片上显示图像的值。

公开(公告)号：US20050105797A1

公开(公告)日：2005-05-19

申请号：US11022165

申请日：2004-12-23

申请人： Arun Rao

发明人： Arun Rao

IPC分类号： G06T11/00 ,  G06F15/00 ,  G06K9/00

CPC分类号： G06T11/001

摘要： A system for efficiently converting computer graphics images to film images with accurate color management is described. The system involves the creation of a direct mapping of chromaticity and intensity data from the values used to generate images on a computer monitor to the values used to display the images on projected motion picture film.

公开(公告)号：US07395300B2

公开(公告)日：2008-07-01

申请号：US10765614

申请日：2004-01-27

申请人： Sunoj Koshy ,  Arun Rao

发明人： Sunoj Koshy ,  Arun Rao

IPC分类号： G06F7/52

CPC分类号： G06F1/0307

摘要： Presented herein are systems and methods for computing the product of a constant and a mixed number power of two. A circuit comprises a first register, a second register, a memory, a third register, and a multiplier circuit. The first register stores the constant. The second register stores the integer portion and the fraction portion. The memory stores a plurality of values, each of said plurality of values corresponding to a particular one of a corresponding plurality of fractions, wherein each one of said plurality of values is two to the exponential fraction corresponding to the one of said plurality of values. The third register stores a particular one of the plurality of values, said particular one of the plurality of values corresponding to the fraction portion. The multiplier circuit multiplies the contents of the third register by the contents of the first register, thereby resulting in a product. The product is shifted a certain number of times, the certain number of times equal to the integer portion.

摘要翻译： 这里提出的是用于计算两个恒定和混合数量幂的乘积的系统和方法。 电路包括第一寄存器，第二寄存器，存储器，第三寄存器和乘法器电路。 第一个寄存器存储常量。 第二个寄存器存储整数部分和分数部分。 存储器存储多个值，所述多个值中的每一个值对应于对应的多个分数中的特定值，其中所述多个值中的每一个值对应于所述多个值中的一个值的指数分数为2。 第三寄存器存储多个值中的特定值，所述多个值中的特定值对应于分数部分。 乘法器电路将第三寄存器的内容乘以第一寄存器的内容，从而产生一个乘积。 产品移动一定次数，一定次数等于整数部分。

公开(公告)号：US20050165877A1

公开(公告)日：2005-07-28

申请号：US10765614

申请日：2004-01-27

申请人： Sunoj Koshy ,  Arun Rao

发明人： Sunoj Koshy ,  Arun Rao

IPC分类号： G06F1/03 ,  G06F7/52

CPC分类号： G06F1/0307

摘要： Presented herein are systems and methods for computing the product of a constant and a mixed number power of two. A circuit comprises a first register, a second register, a memory, a third register, and a multiplier circuit. The first register stores the constant. The second register stores the integer portion and the fraction portion. The memory stores a plurality of values, each of said plurality of values corresponding to a particular one of a corresponding plurality of fractions, wherein each one of said plurality of values is two to the exponential fraction corresponding to the one of said plurality of values. The third register stores a particular one of the plurality of values, said particular one of the plurality of values corresponding to the fraction portion. The multiplier circuit multiplies the contents of the third register by the contents of the first register, thereby resulting in a product. The product is shifted a certain number of times, the certain number of times equal to the integer portion.

摘要翻译： 这里提出的是用于计算两个恒定和混合数量幂的乘积的系统和方法。 电路包括第一寄存器，第二寄存器，存储器，第三寄存器和乘法器电路。 第一个寄存器存储常量。 第二个寄存器存储整数部分和分数部分。 存储器存储多个值，所述多个值中的每一个值对应于对应的多个分数中的特定值，其中所述多个值中的每一个值对应于所述多个值中的一个值的指数分数为2。 第三寄存器存储多个值中的特定值，所述多个值中的特定值对应于分数部分。 乘法器电路将第三寄存器的内容乘以第一寄存器的内容，从而产生一个乘积。 产品移动一定次数，一定次数等于整数部分。

公开(公告)号：US06895110B2

公开(公告)日：2005-05-17

申请号：US10699561

申请日：2003-10-30

申请人： Arun Rao

发明人： Arun Rao

IPC分类号： G06T11/00 ,  G06K9/00 ,  G06F13/00

CPC分类号： G06T11/001

摘要： A system for efficiently converting computer graphics images to film images with accurate color management is described. The system involves the creation of a direct mapping of chromaticity and intensity data from the values used to generate images on a computer monitor to the values used to display the images on projected motion picture film.

摘要翻译： 描述了一种用于将计算机图形图像有效地转换成具有精确颜色管理的胶片图像的系统。 该系统包括从用于在计算机监视器上生成图像的值的色度和强度数据的直接映射到用于在投影电影胶片上显示图像的值。

公开(公告)号：US20050096918A1

公开(公告)日：2005-05-05

申请号：US10725771

申请日：2003-12-02

申请人： Arun Rao ,  Sunoj Koshy

发明人： Arun Rao ,  Sunoj Koshy

IPC分类号： G10L19/14 ,  G10L19/00

CPC分类号： G10L19/16

摘要： Presented herein is a method and system for reducing the total memory required by an audio decoding device by providing audio decoder buffer optimization, memory overwriting capability during audio decoding, and ordered processing of audio decoder program operations. Memory may be reduced by applying the buffer overlaying method to reduce the amount of memory to perform audio decoding to a minimum amount of memory. Audio decoding devices implementing the memory reducing method may be provided with a minimum amount of memory, reducing the cost of the audio decoding devices while efficiently decoding audio signals.

摘要翻译： 这里提出了一种通过在音频解码期间提供音频解码器缓冲器优化，存储器重写能力以及音频解码器程序操作的有序处理来减少音频解码装置所需的总存储器的方法和系统。 可以通过应用缓冲覆盖方法来减少存储器，以将执行音频解码的存储器的量减少到最小量的存储器。 实现存储器减少方法的音频解码装置可以提供最小量的存储器，从而降低音频解码装置的成本，同时有效地解码音频信号。

公开(公告)号：US5631981A

公开(公告)日：1997-05-20

申请号：US614446

申请日：1996-03-12

申请人： Arun Rao

发明人： Arun Rao

IPC分类号： G06T7/60 ,  G06K9/64 ,  G06T3/00

CPC分类号： G06T3/0093 ,  G06K9/6206

摘要： A template useful in registering an incoming bitmapped image with a master bitmapped image is created by convolving the master with a Gaussian function and computing the gradient of the resulting scalar field. According to the invention, the incoming image is iteratively moved with respect to the template in response to the gradient of the scalar field formed by the convolution operation, i.e., the direction of adjustment is a function of the gradient of the scalar field formed by the convolution operation used to create the template. According to one embodiment of the invention, the registration process is terminated when the error between the master and the image is below a predefined threshold.

摘要翻译： 通过用高斯函数卷积主机并计算所得到的标量字段的梯度，创建了用于通过主位映射图像注册输入位图图像的模板。 根据本发明，响应于通过卷积运算形成的标量场的梯度，输入图像相对于模板被迭代地移动，即，调整方向是由由该曲线形成的标量场的梯度的函数 卷积操作用于创建模板。 根据本发明的一个实施例，当主机和图像之间的误差低于预定阈值时，注册过程终止。

公开(公告)号：US09240073B2

公开(公告)日：2016-01-19

申请号：US13323027

申请日：2011-12-12

申请人： Arun Rao ,  Frank Grassia ,  Michael O'Brien ,  Michael Shantzis ,  Paul Edmondson

发明人： Arun Rao ,  Frank Grassia ,  Michael O'Brien ,  Michael Shantzis ,  Paul Edmondson

IPC分类号： G06T17/00 ,  G06T13/00

CPC分类号： G06T13/00 ,  G06F17/30126 ,  G06F17/30327 ,  G06T17/00 ,  G06T2210/32

摘要： A file format that includes a constant section and a varying section. The constant section provides a referencing scheme that references the various components that comprise the scene, as well as a listing of attributes of the scene that are modifiable. Within the same file format, the varying section provides an overriding mechanism to modify the attributes that are available to be modified. Accordingly, the disclosed file format can access cached animated geometry directly and/or aggregate other files via the aforementioned referencing and sparse override semantics. This allows the same set of inspection, manipulation, and rendering tools to be used throughout the rendering pipeline, from asset creation to final rendering.

摘要翻译： 包含常数部分和变化部分的文件格式。 常数部分提供了引用构成场景的各种组件的引用方案，以及可修改的场景的属性列表。 在相同的文件格式中，变化部分提供了一种重写机制来修改可修改的属性。 因此，所公开的文件格式可以经由上述引用和稀疏覆盖语义直接访问缓存的动画几何和/或聚合其他文件。 这允许在整个渲染流程中使用相同的检查，操作和渲染工具集，从资产创建到最终渲染。

公开(公告)号：US20130120422A1

公开(公告)日：2013-05-16

申请号：US13323027

申请日：2011-12-12

申请人： Arun RAO ,  Frank GRASSIA ,  Michael O'Brien ,  Michael SHANTZIS ,  Paul EDMONDSON

发明人： Arun RAO ,  Frank GRASSIA ,  Michael O'Brien ,  Michael SHANTZIS ,  Paul EDMONDSON

IPC分类号： G09G5/00

CPC分类号： G06T13/00 ,  G06F17/30126 ,  G06F17/30327 ,  G06T17/00 ,  G06T2210/32

摘要： A file format that includes a constant section and a varying section. The constant section provides a referencing scheme that references the various components that comprise the scene, as well as a listing of attributes of the scene that are modifiable. Within the same file format, the varying section provides an overriding mechanism to modify the attributes that are available to be modified. Accordingly, the disclosed file format can access cached animated geometry directly and/or aggregate other files via the aforementioned referencing and sparse override semantics. This allows the same set of inspection, manipulation, and rendering tools to be used throughout the rendering pipeline, from asset creation to final rendering.

摘要翻译： 包含常数部分和变化部分的文件格式。 常数部分提供了引用构成场景的各种组件的引用方案，以及可修改的场景的属性列表。 在相同的文件格式中，变化部分提供了一种重写机制来修改可修改的属性。 因此，所公开的文件格式可以经由上述引用和稀疏覆盖语义直接访问缓存的动画几何和/或聚合其他文件。 这允许在整个渲染流程中使用相同的检查，操作和渲染工具集，从资产创建到最终渲染。

公开(公告)号：US07456677B1

公开(公告)日：2008-11-25

申请号：US11381101

申请日：2006-05-01

申请人： Arun Rao ,  John Philip Parry ,  William J. McIntyre ,  Nathanael Griesert

发明人： Arun Rao ,  John Philip Parry ,  William J. McIntyre ,  Nathanael Griesert

IPC分类号： G05F1/10

CPC分类号： H02M3/07 ,  H02M2001/0045

摘要： A switch array circuit that enables voltage regulation by bucking a relatively larger input voltage as it declines over time with different fractional gains that are based on different gain phase arrangements for a plurality of capacitors. A common rest phase is provided during the switching between the different gain phases. The rest phase inherently enables power to be conserved during gain transitions. Increasingly larger fractional gain phases (less buck) is provided as the input voltage declines over time, e.g., from ⅓ to ⅖ to ½ to ⅔ to unity, and the like. Also, the common rest phase for the plurality of capacitors is arranged to minimize fluctuation of the output voltage during switching between phases to generate a selected gain from the gain phase. Additionally, the common rest phase conserves/stores energy during switching transitions between multiple gain phases. The stored energy in the common rest phase can be subsequently reused in the gain phases.

摘要翻译： 一种开关阵列电路，其通过抵抗相对较大的输入电压来实现电压调节，因为随着时间的推移不同，分数增益基于多个电容器的不同的增益相位布置而降低。 在不同增益阶段之间的切换期间提供常见的休止阶段。 其余阶段固有地使功率在增益转换期间得以节约。 随着输入电压随时间的推移而下降，例如从1/3到2/5到1/2到2/3等于1，提供越来越大的分数增益相位（更小的降压）。 此外，多个电容器的共用静止相位被布置为使相间切换期间的输出电压的波动最小化，以从增益阶段产生选定的增益。 另外，在多个增益阶段之间的切换转换期间，常用的休止阶段保存/存储能量。 共用静止阶段中的存储能量可以随后在增益阶段重新使用。