公开(公告)号：US07015116B1

公开(公告)日：2006-03-21

申请号：US10897601

申请日：2004-07-23

申请人： Guo-Qiang (Patrick) Lo ,  Brian Schorr ,  Gary Foley ,  Shih-Ked Lee

发明人： Guo-Qiang (Patrick) Lo ,  Brian Schorr ,  Gary Foley ,  Shih-Ked Lee

IPC分类号： H01L21/76

CPC分类号： H01L21/764 ,  H01L21/76224

摘要： A shallow trench isolation (STI) structure in a semiconductor substrate and a method for forming the same are provided. A trench is formed in a semiconductor substrate. A first dielectric layer is formed on sidewalls of the trench. The first dielectric layer is formed thicker at a top portion of the sidewalls than a bottom portion of the sidewalls and leaving an entrance of the trench open to expose the trench. A second dielectric layer is conformally formed on the first dielectric layer to close the entrance, thus forming a void buried within the trench. Thus, the stress between the trench dielectric layer and the surrounding silicon substrate during thermal cycling can be substantially reduced.

摘要翻译： 提供半导体衬底中的浅沟槽隔离（STI）结构及其形成方法。 在半导体衬底中形成沟槽。 第一电介质层形成在沟槽的侧壁上。 第一电介质层在侧壁的顶部处形成得比侧壁的底部更厚，并且使沟槽的入口敞开以暴露沟槽。 在第一电介质层上共形形成第二电介质层以封闭入口，从而形成埋在沟槽内的空隙。 因此，可以显着地减少在热循环期间沟槽电介质层和周围硅衬底之间的应力。

公开(公告)号：US06791155B1

公开(公告)日：2004-09-14

申请号：US10251550

申请日：2002-09-20

申请人： Guo-Qiang (Patrick) Lo ,  Brian Schorr ,  Gary Foley ,  Shih-Ked Lee

发明人： Guo-Qiang (Patrick) Lo ,  Brian Schorr ,  Gary Foley ,  Shih-Ked Lee

IPC分类号： H01L2176

CPC分类号： H01L21/764 ,  H01L21/76224

摘要： A shallow trench isolation (STI) structure in a semiconductor substrate and a method for forming the same are provided. A trench is formed in a semiconductor substrate. A first dielectric layer is formed on sidewalls of the trench. The first dielectric layer is formed thicker at a top portion of the sidewalls than a bottom portion of the sidewalls and leaving an entrance of the trench open to expose the trench. A second dielectric layer is conformally formed on the first dielectric layer to close the entrance, thus forming a void buried within the trench. Thus, the stress between the trench dielectric layer and the surrounding silicon substrate during thermal cycling can be substantially reduced.

摘要翻译： 提供半导体衬底中的浅沟槽隔离（STI）结构及其形成方法。 在半导体衬底中形成沟槽。 第一电介质层形成在沟槽的侧壁上。 第一电介质层在侧壁的顶部处形成得比侧壁的底部更厚，并且使沟槽的入口敞开以暴露沟槽。 在第一电介质层上共形形成第二电介质层以封闭入口，从而形成埋在沟槽内的空隙。 因此，可以显着地减少在热循环期间沟槽电介质层和周围硅衬底之间的应力。