公开(公告)号：US20050251646A1

公开(公告)日：2005-11-10

申请号：US10829646

申请日：2004-04-21

申请人： Mark Klecka ,  Kamal Khadiri ,  Robert Patti ,  Derrick Wilson ,  Lee Hoyman ,  Bruce Tyda

发明人： Mark Klecka ,  Kamal Khadiri ,  Robert Patti ,  Derrick Wilson ,  Lee Hoyman ,  Bruce Tyda

IPC分类号： G06F15/00 ,  H04L12/40

CPC分类号： H04L12/40

摘要： A circuit having an interconnect network and plurality of processing blocks is disclosed. The interconnect network has a plurality of network nodes arranged in a two-dimensional array on a first substrate. Each network node has a plurality of communication ports and is connected to each adjacent network node by a communication bus that connects only those two network nodes and processing blocks adjacent to that communication bus. A programmable switch within each node connects one of the input ports to one of the output ports in response to connection information stored in a memory in that node. Three-dimensional embodiments can be constructed by including a second substrate that overlies the first substrate and includes a second such interconnect network that is connected vertically through one or more nodes. The circuit easily accommodates spare processing blocks that can be substituted for defective blocks by altering the connection information.

摘要翻译： 公开了具有互连网络和多个处理块的电路。 互连网络具有在第一基板上以二维阵列布置的多个网络节点。 每个网络节点具有多个通信端口，并且通过仅连接那些两个网络节点和与该通信总线相邻的处理块的通信总线连接到每个相邻的网络节点。 响应于存储在该节点中的存储器中的连接信息，每个节点内的可编程开关将一个输入端口连接到其中一个输出端口。 可以通过包括覆盖在第一衬底上的第二衬底并且包括通过一个或多个节点垂直连接的第二这样的互连网络来构造三维实施例。 该电路容易地容纳可以通过改变连接信息来代替有缺陷的块的备用处理块。

公开(公告)号：US07159047B2

公开(公告)日：2007-01-02

申请号：US10829646

申请日：2004-04-21

申请人： Mark Klecka ,  Kamal Khadiri ,  Robert Patti ,  Derrick Brent Wilson ,  Lee Hoyman ,  Bruce Tyda

发明人： Mark Klecka ,  Kamal Khadiri ,  Robert Patti ,  Derrick Brent Wilson ,  Lee Hoyman ,  Bruce Tyda

IPC分类号： G06F13/00

CPC分类号： H04L12/40

摘要： A circuit having an interconnect network and plurality of processing blocks is disclosed. The interconnect network has a plurality of network nodes arranged in a two-dimensional array on a first substrate. Each network node has a plurality of communication ports and is connected to each adjacent network node by a communication bus that connects only those two network nodes and processing blocks adjacent to that communication bus. A programmable switch within each node connects one of the input ports to one of the output ports in response to connection information stored in a memory in that node. Three-dimensional embodiments can be constructed by including a second substrate that overlies the first substrate and includes a second such interconnect network that is connected vertically through one or more nodes. The circuit easily accommodates spare processing blocks that can be substituted for defective blocks by altering the connection information.

摘要翻译： 公开了具有互连网络和多个处理块的电路。 互连网络具有在第一基板上以二维阵列布置的多个网络节点。 每个网络节点具有多个通信端口，并且通过仅连接那些两个网络节点和与该通信总线相邻的处理块的通信总线连接到每个相邻的网络节点。 响应于存储在该节点中的存储器中的连接信息，每个节点内的可编程开关将一个输入端口连接到其中一个输出端口。 可以通过包括覆盖在第一衬底上的第二衬底并且包括通过一个或多个节点垂直连接的第二这样的互连网络来构造三维实施例。 该电路容易地容纳可以通过改变连接信息来代替有缺陷的块的备用处理块。