摘要:
A method, apparatus and computer program product for synthesizing and correcting ESD and EOS ground rules faults in integrated circuits generates a representation of a first functional circuit element (e.g., logic gate) connected to a representation of a first input/output (I/O) pad, via a representation of a first electrical path, and generates a representation of a first ESD circuit element connected to the representation of the first input/output pad via a representation of a second electrical path which may overlap a portion of the first electrical path. First and second sheet resistances (or quantities related thereto) of the first and second electrical paths, respectively, are determined and a length and/or width of the representation of at least one of the first and second electrical paths is adjusted if the first sheet resistance is greater than the second sheet resistance, so that the first sheet resistance is less than the second sheet resistance. Corners in representations of adjacent power rails are also detected, where these representations have opposing edges separated by a minimum rail spacing, and a position of at least one of the power rails relative to the other is adjusted so that the opposing edges are separated by a spacing which is no less than about two times the minimum rail spacing.
摘要:
A method for forming FET devices with attenuated gate induced drain leakage current. There is provided a silicon semiconductor substrate employed within a microelectronics fabrication. There is formed within the silicon substrate field oxide (FOX) dielectric isolation regions defining an active silicon substrate device area. There is formed over the substrate a silicon oxide gate oxide insulation layer employing thermal oxidation. There is then formed over the silicon oxide gate oxide insulation layer a patterned polycrystalline silicon gate electrode layer. There is then thermally oxidized the substrate and polycrystalline silicon gate electrode to form a thicker silicon oxide layer at the edge of the gate electrode and in the adjacent silicon substrate area. There is then etched back the thicker silicon oxide layer from the silicon substrate area adjacent to the gate electrode. There is then formed employing low energy ion implantation shallow junction source-drain extension regions adjacent to the gate electrode. There is then formed source-drain regions to complete the FET device, which exhibits attenuated drain leakage current. The present invention may be employed to fabricate complementary metal-oxide-silicon (CMOS) FET devices of either polarity with attenuated gate induced drain leakage (GIDL) current, short channel effect (SCE) and punch-through leakage current in integrated circuit microelectronics fabrications wherein low power drain is desired.