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公开(公告)号：US20120286850A1
公开(公告)日：2012-11-15
申请号：US13067183
申请日：2011-05-13
IPC分类号： G11C5/14
CPC分类号： G11C14/0054
摘要： Apparatus for storing a data value in the form of a master-slave latch supporting zig-zag power gating is described. A NAND gate 52 at the output of the latch forces a predetermined retention signal value at the output from the latch during a retention mode. A scan multiplexer 42 at the input to the latch selects the scan input, which is the predetermined retention signal from another latch, during the retention mode. Within the latch power gated circuitry 32 is subject to zig-zag power gating using virtual power rails VDDZ and VSSZ so as to reduce the leakage current. State storing circuitry 34 is permanently connected to the power supplies VDDG, VSSG such that it is able to maintain whatever signal value is stored therein during the retention mode.
摘要翻译： 描述了以支持Z形电源门控的主从锁存器的形式存储数据值的装置。 在锁存器的输出处的NAND门52在保持模式期间迫使来自锁存器的输出处的预定保持信号值。 在锁存器的输入处的扫描多路复用器42在保持模式期间选择作为来自另一锁存器的预定保持信号的扫描输入。 在闩锁电源选通电路32内，使用虚拟电源轨VDDZ和VSSZ进行Z形电源门控，以减少漏电流。 状态存储电路34永久地连接到电源VDDG，VSSG，使得能够在保持模式期间保持其中存储的任何信号值。
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公开(公告)号：US08451039B2
公开(公告)日：2013-05-28
申请号：US13067183
申请日：2011-05-13
IPC分类号： H03K3/289
CPC分类号： G11C14/0054
摘要： Apparatus for storing a data value in the form of a master-slave latch supporting zig-zag power gating is described. A NAND gate 52 at the output of the latch forces a predetermined retention signal value at the output from the latch during a retention mode. A scan multiplexer 42 at the input to the latch selects the scan input, which is the predetermined retention signal from another latch, during the retention mode. Within the latch power gated circuitry 32 is subject to zig-zag power gating using virtual power rails VDDZ and VSSZ so as to reduce the leakage current. State storing circuitry 34 is permanently connected to the power supplies VDDG, VSSG such that it is able to maintain whatever signal value is stored therein during the retention mode.
摘要翻译： 描述了以支持Z形电源门控的主从锁存器的形式存储数据值的装置。 在锁存器的输出处的NAND门52在保持模式期间迫使来自锁存器的输出处的预定保持信号值。 在锁存器的输入处的扫描多路复用器42在保持模式期间选择作为来自另一锁存器的预定保持信号的扫描输入。 在闩锁电源门控电路32内，使用虚拟电源线VDDZ和VSSZ进行Z形电源门控，以减少漏电流。 状态存储电路34永久地连接到电源VDDG，VSSG，使得能够在保持模式期间保持其中存储的任何信号值。
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3.发明授权Integrated circuit, method of generating a layout of an integrated circuit using standard cells, and a standard cell library providing such standard cells 有权集成电路，使用标准单元生成集成电路的布局的方法以及提供这种标准单元的标准单元库公开(公告)号：US08451026B2
公开(公告)日：2013-05-28
申请号：US13067182
申请日：2011-05-13
申请人： John Philip Biggs , James Edward Myers , David William Howard , David Walter Flynn , Carsten Tradowsky
发明人： John Philip Biggs , James Edward Myers , David William Howard , David Walter Flynn , Carsten Tradowsky
CPC分类号： H01L27/0207 , G06F17/5068 , G06F17/5072 , G06F2217/78 , H01L27/11807 , H01L2027/11881
摘要： An integrated circuit, a method of generating a layout of such an integrated circuit using standard cells, and a standard cell library providing such standard cells, are disclosed. The method of generating the layout comprises forming a plurality of rows, and populating each row with a plurality of standard cells chosen in dependence on the functional components required by the integrated circuit, each standard cell having its abutment area abutting the abutment area of at least one adjacent standard cell in the row. Within each row, each standard cell in that row is arranged to have a voltage connection area that is aligned with a common routing track, but with each standard cell having its voltage connection area configured so as not to extend across the entire width of the standard cell. Within each row, for each standard cell in the row, the voltage connection area of that standard cell is then connected to one of a plurality of voltage supplies having regards to a voltage requirement of the corresponding functional component defined by the standard cell, and independent of the voltage supply to which each adjacent cell in the row is connected. This provides a particularly flexible mechanism for placing standard cells during the layout operation, since standard cells that are required to run off the same voltage supply no longer need to be placed together.
摘要翻译： 公开了集成电路，使用标准单元生成这种集成电路的布局的方法以及提供这种标准单元的标准单元库。 生成布局的方法包括形成多个行，并且根据集成电路所需的功能部件选择多个标准单元填充每行，每个标准单元具有邻接至少的邻接区域的邻接区域 行中一个相邻的标准单元格。 在每排中，该行中的每个标准单元被布置成具有与公共路线轨迹对准的电压连接区域，但是每个标准单元具有其电压连接区域被配置为不在标准的整个宽度上延伸 细胞。 在每排中，对于行中的每个标准单元，该标准单元的电压连接区域然后连接到关于由标准单元定义的相应功能组件的电压要求的多个电压源中的一个，并且独立 的每个相邻单元连接到的电压源。 这为布局操作期间放置标准单元提供了一种特别灵活的机制，因为运行相同电压源所需的标准单元不再需要放在一起。
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4.发明申请Integrated circuit, method of generating a layout of an integrated circuit using standard cells, and a standard cell library providing such standard cells 有权集成电路，使用标准单元生成集成电路的布局的方法以及提供这种标准单元的标准单元库公开(公告)号：US20120286858A1
公开(公告)日：2012-11-15
申请号：US13067182
申请日：2011-05-13
申请人： John Philip Biggs , James Edward Myers , David William Howard , David Walter Flynn , Carsten Tradowsky
发明人： John Philip Biggs , James Edward Myers , David William Howard , David Walter Flynn , Carsten Tradowsky
CPC分类号： H01L27/0207 , G06F17/5068 , G06F17/5072 , G06F2217/78 , H01L27/11807 , H01L2027/11881
摘要： An integrated circuit, a method of generating a layout of such an integrated circuit using standard cells, and a standard cell library providing such standard cells, are disclosed. The method of generating the layout comprises forming a plurality of rows, and populating each row with a plurality of standard cells chosen in dependence on the functional components required by the integrated circuit, each standard cell having its abutment area abutting the abutment area of at least one adjacent standard cell in the row. Within each row, each standard cell in that row is arranged to have a voltage connection area that is aligned with a common routing track, but with each standard cell having its voltage connection area configured so as not to extend across the entire width of the standard cell. Within each row, for each standard cell in the row, the voltage connection area of that standard cell is then connected to one of a plurality of voltage supplies having regards to a voltage requirement of the corresponding functional component defined by the standard cell, and independent of the voltage supply to which each adjacent cell in the row is connected. This provides a particularly flexible mechanism for placing standard cells during the layout operation, since standard cells that are required to run off the same voltage supply no longer need to be placed together.
摘要翻译： 公开了集成电路，使用标准单元生成这种集成电路的布局的方法以及提供这种标准单元的标准单元库。 生成布局的方法包括形成多个行，并且根据集成电路所需的功能部件选择多个标准单元填充每行，每个标准单元具有邻接至少的邻接区域的邻接区域 行中一个相邻的标准单元格。 在每排中，该行中的每个标准单元被布置成具有与公共路线轨迹对准的电压连接区域，但是每个标准单元具有其电压连接区域被配置为不在标准的整个宽度上延伸 细胞。 在每排中，对于行中的每个标准单元，该标准单元的电压连接区域然后连接到关于由标准单元定义的相应功能组件的电压要求的多个电压源中的一个，并且独立 的每个相邻单元连接到的电压源。 这为布局操作期间放置标准单元提供了一种特别灵活的机制，因为运行相同电压源所需的标准单元不再需要放在一起。
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