Inductive and capacitive elements for semiconductor technologies with minimum pattern density requirements
    1.
    发明授权
    Inductive and capacitive elements for semiconductor technologies with minimum pattern density requirements 有权
    具有最小图案密度要求的半导体技术的感性和电容元件

    公开(公告)号:US08653926B2

    公开(公告)日:2014-02-18

    申请号:US10564582

    申请日:2004-07-15

    IPC分类号: H01F5/00

    摘要: The present invention provides a semiconductor device comprising a plurality of layers, the semiconductor device comprising:—a substrate having a first major surface,—an inductive element fabricated on the first major surface of the substrate, the inductive element comprising at least one conductive line, and—a plurality of tilling structures in at least one layer, wherein the plurality of tilling structures are electrically connected together and are arranged in a geometrical pattern so as to substantially inhibit an inducement of an image current in the tilling structures by a current in the inductive element. It is an advantage of the above semiconductor device that, by using such tilling structures, an inductive element with improved quality factor is obtained. The present invention also provides a method for providing an inductive element in a semiconductor device comprising a plurality of layers.

    摘要翻译: 本发明提供一种包括多个层的半导体器件,所述半导体器件包括: - 具有第一主表面的衬底, - 在所述衬底的第一主表面上制造的电感元件,所述电感元件包括至少一个导线 以及 - 至少一层中的多个耕作结构,其中所述多个耕作结构电连接在一起并且被布置成几何图案,以便基本上禁止通过所述耕作结构中的电流来诱导所述耕作结构中的图像电流 电感元件。 上述半导体器件的优点是,通过使用这种耕作结构,获得了具有改善的品质因数的电感元件。 本发明还提供一种在包括多个层的半导体器件中提供电感元件的方法。