公开(公告)号：US20120173791A1

公开(公告)日：2012-07-05

申请号：US12981499

申请日：2010-12-30

Applicant: Chih-Hung Wang ,  Chao-Han Wu ,  Ting-Chung Hu

Inventor： Chih-Hung Wang ,  Chao-Han Wu ,  Ting-Chung Hu

IPC: G06F12/02

CPC classification number: G06F12/0246

Abstract: A control method and an allocation structure for a flash memory device are provided herein. The flash memory device has a first memory module and a second memory module. Physical blocks of the first memory module and physical blocks of the second memory module are respectively divided into a plurality of groups, each of which has a plurality of the physical blocks. A first subunit and a second subunit of a first allocation unit are interleavingly written into a first group of the groups of the first memory module and a second group of the groups of the second memory chip respectively. Additionally, a first subunit and a second subunit of a second allocation unit are interleavingly written into a third group of the groups of the first memory module and the second group, respectively.

Abstract translation: 本文提供了一种用于闪速存储器件的控制方法和分配结构。 闪存设备具有第一存储器模块和第二存储器模块。 第一存储器模块的物理块和第二存储器模块的物理块分别被分成多个组，每个组具有多个物理块。 第一分配单元的第一子单元和第二子单元分别被交织地写入第一存储器模块的组的第一组和第二存储器芯片的组的第二组。 此外，第二分配单元的第一子单元和第二子单元分别被交织地写入第一存储器模块和第二组的组的第三组中。

公开(公告)号：US08713242B2

公开(公告)日：2014-04-29

申请号：US12981499

申请日：2010-12-30

Applicant: Chih-Hung Wang ,  Chao-Han Wu ,  Ting-Chung Hu

Inventor： Chih-Hung Wang ,  Chao-Han Wu ,  Ting-Chung Hu

IPC: G06F12/02

CPC classification number: G06F12/0246

Abstract: A control method and an allocation structure for a flash memory device are provided herein. The flash memory device has a first memory module and a second memory module. Physical blocks of the first memory module and physical blocks of the second memory module are respectively divided into a plurality of groups, each of which has a plurality of the physical blocks. A first subunit and a second subunit of a first allocation unit are interleavingly written into a first group of the groups of the first memory module and a second group of the groups of the second memory chip respectively. Additionally, a first subunit and a second subunit of a second allocation unit are interleavingly written into a third group of the groups of the first memory module and the second group, respectively.

Abstract translation: 本文提供了一种用于闪速存储器件的控制方法和分配结构。 闪存设备具有第一存储器模块和第二存储器模块。 第一存储器模块的物理块和第二存储器模块的物理块分别被分成多个组，每个组具有多个物理块。 第一分配单元的第一子单元和第二子单元分别被交织地写入第一存储器模块的组的第一组和第二存储器芯片的组的第二组。 此外，第二分配单元的第一子单元和第二子单元分别被交织地写入第一存储器模块和第二组的组的第三组中。