Self testing CMOS imager chip
    1.
    发明授权
    Self testing CMOS imager chip 有权
    自检CMOS成像芯片

    公开(公告)号:US07053352B2

    公开(公告)日:2006-05-30

    申请号:US10784490

    申请日:2004-02-23

    IPC分类号: H01L27/00

    摘要: A self testing CMOS imager chip includes a controller which outputs a sewer signal, a dump signal, a collect signal, and a read signal, and a pixel array connected to the controller including a plurality of pixels arranged in an array of rows and columns, each pixel having a collect gate disposed adjacent a collect well for receiving a charge in response to application of the collect signal to the collect gate, a sewer for injecting a charge into the collect well in response to the concurrent application of the sewer signal to the sewer and the collect signal to the collect well, a read gate disposed adjacent a read well for receiving the injected charge from the collect well in response to application of the read signal to the read gate and the absence of the collect signal at the collect gate, and a transistor having a gate coupled to the read well, a source for receiving the read signal, and a drain coupled to an output node connected to the controller. The read signal is modulated by the injected charge at the gate of the transistor, thereby generating an injected output signal at the output node representing the injected charge. The controller, through read-out circuitry, comparing the injected output signal to an expected output signal to test the operation of each pixel of the array.

    摘要翻译: 自检CMOS成像器芯片包括输出下水道信号,转储信号,收集信号和读取信号的控制器,以及连接到控制器的像素阵列,该像素阵列包括排列成行和列的阵列的多个像素, 每个像素具有设置在收集井附近的收集门,用于响应于将收集信号应用于收集门而接收电荷;下水道,用于响应于将下水道信号同时施加到收集井而将电荷注入到收集井中 下水道和收集信号到收集井,读门被布置在读取井附近,以响应于读取信号施加到读取门并且在收集门处不存在收集信号从收集井接收注入的电荷 以及晶体管,其具有耦合到所述读取阱的栅极,用于接收所述读取信号的源极和耦合到连接到所述控制器的输出节点的漏极。 读取信号由晶体管栅极处注入的电荷调制,从而在输出节点处产生一个注入的输出信号,代表注入的电荷。 控制器通过读出电路将注入的输出信号与期望的输出信号进行比较,以测试阵列的每个像素的操作。