公开(公告)号：US08860181B2

公开(公告)日：2014-10-14

申请号：US13413669

申请日：2012-03-07

申请人： Ming-Te Wei ,  Po-Chao Tsao ,  Chen-Hua Tsai ,  Chien-Yang Chen ,  Chia-Jui Liang ,  Ming-Tsung Chen

发明人： Ming-Te Wei ,  Po-Chao Tsao ,  Chen-Hua Tsai ,  Chien-Yang Chen ,  Chia-Jui Liang ,  Ming-Tsung Chen

IPC分类号： H01L29/00

CPC分类号： H01L23/5228 ,  H01L29/7833 ,  H01L2924/0002 ,  H01L2924/00

摘要： A thin film resistor structure includes a substrate, a flat bottom ILD (inter layer dielectric) disposed on the substrate, a plurality of first contacts disposed in the bottom ILD, and each top surface of the first contacts is on the same level as a top surface of the bottom ILD; a flat top ILD disposed on the bottom ILD, a plurality of second contacts disposed in the top ILD, and each top surface of the second contacts is on the same level as a top surface of the top ILD, and a thin film resistor disposed between the bottom ILD and the top ILD.

摘要翻译： 薄膜电阻器结构包括基板，设置在基板上的平坦底部ILD（层间电介质），设置在底部ILD中的多个第一触点，并且第一触点的每个顶表面与顶部 底部ILD的表面; 设置在底部ILD上的平顶部ILD，设置在顶部ILD中的多个第二触点，并且第二触点的每个顶部表面位于与顶部ILD的顶表面相同的水平面上，并且薄膜电阻器设置在 底部ILD和顶部ILD。

公开(公告)号：US20130234292A1

公开(公告)日：2013-09-12

申请号：US13413669

申请日：2012-03-07

申请人： Ming-Te Wei ,  Po-Chao Tsao ,  Chen-Hua Tsai ,  Chien-Yang Chen ,  Chia-Jui Liang ,  Ming-Tsung Chen

发明人： Ming-Te Wei ,  Po-Chao Tsao ,  Chen-Hua Tsai ,  Chien-Yang Chen ,  Chia-Jui Liang ,  Ming-Tsung Chen

IPC分类号： H01L29/02

CPC分类号： H01L23/5228 ,  H01L29/7833 ,  H01L2924/0002 ,  H01L2924/00

摘要： A thin film resistor structure includes a substrate, a flat bottom ILD (inter layer dielectric) disposed on the substrate, a plurality of first contacts disposed in the bottom ILD, and each top surface of the first contacts is on the same level as a top surface of the bottom ILD; a flat top ILD disposed on the bottom ILD, a plurality of second contacts disposed in the top ILD, and each top surface of the second contacts is on the same level as a top surface of the top ILD, and a thin film resistor disposed between the bottom ILD and the top ILD.

摘要翻译： 薄膜电阻器结构包括基板，设置在基板上的平坦底部ILD（层间电介质），设置在底部ILD中的多个第一触点，并且第一触点的每个顶表面与顶部 底部ILD的表面; 设置在底部ILD上的平顶部ILD，设置在顶部ILD中的多个第二触点，并且第二触点的每个顶部表面位于与顶部ILD的顶表面相同的水平面上，并且薄膜电阻器设置在 底部ILD和顶部ILD。

公开(公告)号：US09136348B2

公开(公告)日：2015-09-15

申请号：US13417337

申请日：2012-03-12

申请人： Ming-Te Wei ,  Shin-Chuan Huang ,  Yu-Hsiang Hung ,  Po-Chao Tsao ,  Chia-Jui Liang ,  Ming-Tsung Chen ,  Chia-Wen Liang

发明人： Ming-Te Wei ,  Shin-Chuan Huang ,  Yu-Hsiang Hung ,  Po-Chao Tsao ,  Chia-Jui Liang ,  Ming-Tsung Chen ,  Chia-Wen Liang

IPC分类号： H01L29/66 ,  H01L29/78 ,  H01L29/165

CPC分类号： H01L29/66492 ,  H01L29/165 ,  H01L29/6656 ,  H01L29/66636 ,  H01L29/7834 ,  H01L29/7848

摘要： A semiconductor structure includes a gate structure disposed on a substrate and having an outer spacer, a recess disposed in the substrate and adjacent to the gate structure, a doped epitaxial material filling up the recess, a cap layer including an undoped epitaxial material and disposed on the doped epitaxial material, a lightly doped drain disposed below the cap layer and sandwiched between the doped epitaxial material and the cap layer, and a silicide disposed on the cap layer and covering the doped epitaxial material to cover the cap layer together with the outer spacer without directly contacting the lightly doped drain.

摘要翻译： 半导体结构包括设置在基板上并具有外部间隔件的栅极结构，设置在基板中并与栅极结构相邻的凹槽，填充凹部的掺杂的外延材料，包括未掺杂的外延材料的盖层， 所述掺杂的外延材料是设置在所述覆盖层下方并且夹在所述掺杂的外延材料和所述覆盖层之间的轻掺杂漏极，以及设置在所述覆盖层上并覆盖所述掺杂外延材料以与所述外部间隔物一起覆盖所述覆盖层的硅化物 而不直接接触轻掺杂的漏极。

公开(公告)号：US20130234261A1

公开(公告)日：2013-09-12

申请号：US13417337

申请日：2012-03-12

申请人： Ming-Te Wei ,  Shin-Chuan Huang ,  Yu-Hsiang Hung ,  Po-Chao Tsao ,  Chia-Jui Liang ,  Ming-Tsung Chen ,  Chia-Wen Liang

发明人： Ming-Te Wei ,  Shin-Chuan Huang ,  Yu-Hsiang Hung ,  Po-Chao Tsao ,  Chia-Jui Liang ,  Ming-Tsung Chen ,  Chia-Wen Liang

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L29/66492 ,  H01L29/165 ,  H01L29/6656 ,  H01L29/66636 ,  H01L29/7834 ,  H01L29/7848

摘要： A semiconductor structure includes a gate structure disposed on a substrate and having an outer spacer, a recess disposed in the substrate and adjacent to the gate structure, a doped epitaxial material filling up the recess, a cap layer including an undoped epitaxial material and disposed on the doped epitaxial material, a lightly doped drain disposed below the cap layer and sandwiched between the doped epitaxial material and the cap layer, and a silicide disposed on the cap layer and covering the doped epitaxial material to cover the cap layer together with the outer spacer without directly contacting the lightly doped drain.