公开(公告)号：US08443032B2

公开(公告)日：2013-05-14

申请号：US12057266

申请日：2008-03-27

Applicant: Chen Hsing Wang ,  Chieh Lin Chuang ,  Cheng Wen Wu

Inventor： Chen Hsing Wang ,  Chieh Lin Chuang ,  Cheng Wen Wu

IPC: G06F7/52

CPC classification number: G06F7/5318 ,  G06F7/57

Abstract: A multiplication circuit generates a product of a matrix and a first scalar when in matrix mode and a product of a second scalar and a third scalar when in scalar mode. The multiplication circuit comprises a sub-product generator, an accumulator and an adder. The adder is configured to sum outputs of the accumulator to generate the product of the first scalar second scalar and the third scalar when in scalar mode. The sub-product generator generates sub-products of the matrix and the first scalar when in matrix mode and sub-products of the second scalar and the third scalar when in scalar mode. The accumulator is configured to generate the product of the matrix and the first scalar by providing save of the multiplication operation of the outputs from the sub-product generator.

Abstract translation: 当在标量模式下，乘法电路以矩阵模式生成矩阵和第一标量的乘积，并且在标量模式下产生第二标量和第三标量的乘积。 乘法电路包括子乘积发生器，累加器和加法器。 加法器被配置为在标量模式下求和累加器的输出以产生第一标量第二标量和第三标量的乘积。 当以标量模式时，子产品生成器以矩阵模式和第二标量和第三标量的子乘积生成矩阵和第一标量的子产物。 累加器被配置为通过提供来自子产品生成器的输出的乘法运算来生成矩阵和第一标量的乘积。

公开(公告)号：US20120311250A1

公开(公告)日：2012-12-06

申请号：US13484251

申请日：2012-05-30

Applicant: Chieh-Lin CHUANG ,  Wen-Hsiane Lin

Inventor： Chieh-Lin CHUANG ,  Wen-Hsiane Lin

IPC: G06F12/00

CPC classification number: G06F12/0623

Abstract: A heterogeneous memory architecture includes a first memory, a second memory and a memory controller. The first memory has a first memory space. The second memory has a second memory space larger than the first memory space. The memory controller is used for accessing common address space of the first memory and the second memory in a 2X-bit bandwidth, and for disabling the first memory and accessing non-common address space of the second memory in opposite to the first memory in a X-bit bandwidth, X being a positive integer.

Abstract translation: 异构存储器架构包括第一存储器，第二存储器和存储器控制器。 第一个内存具有第一个内存空间。 第二存储器具有比第一存储器空间大的第二存储器空间。 存储器控制器用于以2X位带宽访问第一存储器和第二存储器的公共地址空间，并且用于禁用第一存储器并且在第一存储器的相对于第一存储器的第一存储器中访问非公共地址空间 X位带宽，X为正整数。

公开(公告)号：US20090245505A1

公开(公告)日：2009-10-01

申请号：US12057266

申请日：2008-03-27

Applicant: CHEN HSING WANG ,  CHIEH LIN CHUANG ,  CHENG WEN WU

Inventor： CHEN HSING WANG ,  CHIEH LIN CHUANG ,  CHENG WEN WU

IPC: H04L9/28 ,  G06F7/52 ,  G06F17/10

CPC classification number: G06F7/5318 ,  G06F7/57

Abstract: A multiplication circuit generates a product of a matrix and a first scalar when in matrix mode and a product of a second scalar and a third scalar when in scalar mode. The multiplication circuit comprises a sub-product generator, an accumulator and an adder. The adder is configured to sum outputs of the accumulator to generate the product of the first scalar second scalar and the third scalar when in scalar mode. The sub-product generator generates sub-products of the matrix and the first scalar when in matrix mode and sub-products of the second scalar and the third scalar when in scalar mode. The accumulator is configured to generate the product of the matrix and the first scalar by providing save of the multiplication operation of the outputs from the sub-product generator.

Abstract translation: 当在标量模式下，乘法电路以矩阵模式生成矩阵和第一标量的乘积，并且在标量模式下产生第二标量和第三标量的乘积。 乘法电路包括子乘积发生器，累加器和加法器。 加法器被配置为在标量模式下求和累加器的输出以产生第一标量第二标量和第三标量的乘积。 当以标量模式时，子产品生成器以矩阵模式和第二标量和第三标量的子乘积生成矩阵和第一标量的子产物。 累加器被配置为通过提供来自子产品生成器的输出的乘法运算来生成矩阵和第一标量的乘积。