Circuit and method for determining optimal phase combination for startup
of a polyphase DC motor
    1.
    发明授权
    Circuit and method for determining optimal phase combination for startup of a polyphase DC motor 有权
    确定多相直流电机启动的最佳相位组合的电路和方法

    公开(公告)号:US5977734A

    公开(公告)日:1999-11-02

    申请号:US150129

    申请日:1998-09-09

    IPC分类号: H02P6/20 H02P7/00 H02R39/46

    CPC分类号: H02P6/20

    摘要: A circuit for determining an initial winding combination for motor startup of a polyphase dc motor having a transistor driver circuit comprising a plurality of high side winding drivers and low side winding drivers operably connected to first and second voltage sources comprises a current mirror circuit and a plurality of sense FETs each operably connected between one of the voltage sources and the gate of one of the winding driver transistors in each phase combination. The sense FETs are operably connected to one side of the current mirror circuit. The mirror circuit compares the current through the sense FET with a current threshold provided on the other side of the current mirror and produces an output signal when the threshold is reached. At the same time, the time to reach the threshold is measured and the phase combination having the longest time is stored. Also when the threshold is reached, the sequencer advances to the next phase combination for measurement until all phase combination have been sequenced. The motor is then started with the phase combination having the longest time measurement energized first.

    摘要翻译: 一种用于确定具有晶体管驱动器电路的多相直流电动机的初始绕组组合的电路,该晶体管驱动电路包括可操作地连接到第一和第二电压源的多个高侧绕组驱动器和低侧绕组驱动器,包括电流镜电路和多个 每个相位组合中的每个可操作地连接在一个电压源和一个绕组驱动器晶体管的栅极之间的感测FET。 感测FET可操作地连接到电流镜电路的一侧。 镜像电路将通过感测FET的电流与设置在电流镜的另一侧上的电流阈值进行比较,并在达到阈值时产生输出信号。 同时,测量达到阈值的时间,并存储具有最长时间的相位组合。 此外,当达到阈值时,定序器前进到下一个相位组合进行测量,直到所有相位组合都被排序。 然后,首先通过最长时间测量的相位组合起动电动机。

    Power down brake latch circuit for a brushless DC motor
    2.
    发明授权
    Power down brake latch circuit for a brushless DC motor 失效
    无刷直流电机的掉电制动器锁存电路

    公开(公告)号:US6005359A

    公开(公告)日:1999-12-21

    申请号:US874868

    申请日:1997-06-13

    CPC分类号: G11B19/22

    摘要: A power down brake latch circuit for dynamically braking a spindle motor in a disk drive system is disclosed. The power down brake latch circuit includes a reservoir capacitor, a smoothing capacitor, a timing circuit, and a logic circuit. The timing circuit includes a voltage divider and a bandgap comparator. The smoothing capacitor absorbs a BEMF voltage from the spindle motor as it rotates after losing power. The timing circuit generates a first signal when a voltage on the smoothing capacitor falls below a threshold. The logic circuit brakes the spindle motor in response to the loss of power and the generation of the first signal.

    摘要翻译: 公开了一种用于动态地制动磁盘驱动系统中的主轴电动机的停电制动器闩锁电路。 断电制动器锁存电路包括储存电容器,平滑电容器,定时电路和逻辑电路。 定时电路包括分压器和带隙比较器。 平滑电容器在失去电源后旋转时吸收主轴电机的BEMF电压。 当平滑电容器上的电压下降到阈值以下时,定时电路产生第一信号。 逻辑电路响应于功率的损失和第一信号的产生而制动主轴电动机。