公开(公告)号：US08222679B2

公开(公告)日：2012-07-17

申请号：US12593493

申请日：2008-03-26

Applicant: Thomas Uhlig ,  Felix Fuernhammer ,  Christoph Ellmers

Inventor： Thomas Uhlig ,  Felix Fuernhammer ,  Christoph Ellmers

IPC: H01L29/66

CPC classification number: H01L27/22 ,  G01R33/07 ,  H01L43/065

Abstract: A semiconductor device with an integrated circuit on a semiconductor substrate comprises a Hall effect sensor in a first active region and a lateral high voltage MOS transistor in a second active region. The semiconductor device of the present invention is characterized in that the structure of the integrated Hall effect sensor is strongly related with the structure of a high-voltage DMOS transistor. The integrated Hall effect sensor is in some features similar to a per se known high-voltage DMOS transistor having a double RESURF structure. The control contacts of the Hall effect sensor correspond to the source and drain contacts of the high-voltage DMOS transistor. The semiconductor device of the present invention allows a simplification of the process integration.

Abstract translation: 在半导体衬底上具有集成电路的半导体器件包括第一有源区中的霍尔效应传感器和第二有源区中的横向高压MOS晶体管。 本发明的半导体器件的特征在于，集成霍尔效应传感器的结构与高电压DMOS晶体管的结构密切相关。 集成的霍尔效应传感器具有与本身已知的具有双重RESURF结构的已知高压DMOS晶体管相似的特征。 霍尔效应传感器的控制触点对应于高压DMOS晶体管的源极和漏极触点。 本发明的半导体器件允许简化工艺集成。

公开(公告)号：US20110127583A1

公开(公告)日：2011-06-02

申请号：US12593493

申请日：2008-03-26

Applicant: Thomas Uhlig ,  Felix Fuernhammer ,  Christoph Ellmers

Inventor： Thomas Uhlig ,  Felix Fuernhammer ,  Christoph Ellmers

IPC: H01L27/22

CPC classification number: H01L27/22 ,  G01R33/07 ,  H01L43/065

Abstract: A semiconductor device with an integrated circuit on a semiconductor substrate comprises a Hall effect sensor in a first active region and a lateral high voltage MOS transistor in a second active region. The semiconductor device of the present invention is characterized in that the structure of the integrated Hall effect sensor is strongly related with the structure of a high-voltage DMOS transistor. The integrated Hall effect sensor is in some features similar to a per se known high-voltage DMOS transistor having a double RESURF structure. The control contacts of the Hall effect sensor correspond to the source and drain contacts of the high-voltage DMOS transistor. The semiconductor device of the present invention allows a simplification of the process integration.

Abstract translation: 在半导体衬底上具有集成电路的半导体器件包括第一有源区中的霍尔效应传感器和第二有源区中的横向高压MOS晶体管。 本发明的半导体器件的特征在于，集成霍尔效应传感器的结构与高电压DMOS晶体管的结构密切相关。 集成的霍尔效应传感器具有与本身已知的具有双重RESURF结构的已知高压DMOS晶体管相似的特征。 霍尔效应传感器的控制触点对应于高压DMOS晶体管的源极和漏极触点。 本发明的半导体器件允许简化工艺集成。

公开(公告)号：US20100311214A1

公开(公告)日：2010-12-09

申请号：US12593310

申请日：2008-03-26

Applicant: Christoph Ellmers ,  Thomas Uhlig ,  Felix Fuernhammer ,  Michael Stoisiek ,  Michael Gross

Inventor： Christoph Ellmers ,  Thomas Uhlig ,  Felix Fuernhammer ,  Michael Stoisiek ,  Michael Gross

IPC: H01L21/8238

CPC classification number: H01L21/823807 ,  H01L21/823814 ,  H01L27/0922

Abstract: The invention relates to a method for the production of a first lateral high-voltage MOS transistor and a second lateral high-voltage MOS transistor complimentary thereto on a substrate, wherein the first and second lateral high-voltage MOS transistors each have a conductivity type opposite a drift region, comprising the steps of providing a substrate of a first conductivity type comprising a first active region for the first lateral high-voltage MOS transistor and a second active region for the second lateral high-voltage MOS transistor, and the producing at least one first doping region of the first conductivity type in the first active region and, on the other hand, in the second active region, a drain extension region of the first conductivity type extending from the substrate surface to the interior of the substrate, which allows a simultaneous implantation of doping material in the first and second active regions through respective mask openings of one and the same mask.

Abstract translation: 本发明涉及一种在衬底上制造第一横向高压MOS晶体管和与之互补的第二横向高压MOS晶体管的方法，其中第一和第二横向高压MOS晶体管各自具有相反的导电类型 漂移区域，包括以下步骤：提供包括第一横向高压MOS晶体管的第一有源区和第二横向高压MOS晶体管的第二有源区的第一导电类型的衬底，并且至少产生 第一有源区中第一导电类型的第一掺杂区域和第二有源区中的第一导电类型的漏极延伸区域从衬底表面延伸到衬底的内部，这允许 通过相同掩模的相应掩模开口同时将掺杂材料注入第一和第二有源区域。

公开(公告)号：US08405157B2

公开(公告)日：2013-03-26

申请号：US12593316

申请日：2008-03-26

Applicant: Thomas Uhlig ,  Felix Fuernhammer ,  Christoph Ellmers

Inventor： Thomas Uhlig ,  Felix Fuernhammer ,  Christoph Ellmers

IPC: H01L29/66

CPC classification number: H01L21/8249 ,  H01L27/0623 ,  H01L27/0883

Abstract: The invention relates to a BiMOS semiconductor component having a semiconductor substrate wherein, in a first active region, a depletion-type MOS transistor is formed comprising additional source and drain doping regions of the first conductivity type extending in the downward direction past the depletion region into the body doping region while, in a second active region, (101), a bipolar transistor (100) is formed, the base of which comprises a body doping region (112) and the collector of which comprises a deep pan (110), wherein an emitter doping region (114) of the first conductivity type and a base connection doping region (118) of the second conductivity type are formed in the body doping region. The semiconductor element can be produced with a particularly low process expenditure because it uses the same basic structure for the doping regions in the bipolar transistor as are used in the MOS transistor of the same semiconductor component.

Abstract translation: 本发明涉及一种具有半导体衬底的BiMOS半导体部件，其中在第一有源区中形成耗尽型MOS晶体管，该耗尽型MOS晶体管包括沿向下方向延伸穿过耗尽区的第一导电类型的额外源极和漏极掺杂区域， 在第二有源区中形成（101）双极晶体管（100）的本体掺杂区域，其基极包括体掺杂区域（112），并且其集电极包括深盘（110）， 其中在所述体内掺杂区域中形成有所述第一导电类型的发射极掺杂区域（114）和所述第二导电类型的基极连接掺杂区域（118）。 由于半导体元件对于双相晶体管中的掺杂区域使用相同的基本结构，就像在同一半导体元件的MOS晶体管中使用的那样，可以制造出特别低的工艺成本。

公开(公告)号：US08207031B2

公开(公告)日：2012-06-26

申请号：US12593310

申请日：2008-03-26

Applicant: Christoph Ellmers ,  Thomas Uhlig ,  Felix Fuernhammer ,  Michael Stoisiek ,  Michael Gross

Inventor： Christoph Ellmers ,  Thomas Uhlig ,  Felix Fuernhammer ,  Michael Stoisiek ,  Michael Gross

IPC: H01L21/8238

CPC classification number: H01L21/823807 ,  H01L21/823814 ,  H01L27/0922

Abstract: Methods of forming, on a substrate, a first lateral high-voltage MOS transistor and a second lateral high-voltage MOS transistor complementary to said first one are disclosed. According to one embodiment, the method includes (1) providing a substrate of a first conductivity type including a first active region for said first lateral high-voltage MOS transistor and a second active region for said second lateral high-voltage MOS transistor and (2) forming at least one first doped region of the first conductivity type in the first active region and forming in the second active region a drain extension region of the second conductivity type extending from a substrate surface to an interior of the substrate, including a concurrent implantation of dopants through openings of one and the same mask into the first and second active regions. Forming of the at least one first doped region may be a sub step of a superior step of forming a double RESURF structure in the first lateral high-voltage MOS transistor, and forming the double RESURF structure may include forming doped RESURF regions as two first doped regions, one thereof above and one thereof below the drift region of the first lateral high-voltage MOS transistor, and as two further doped regions, one thereof above and one thereof below the drain extension regions of the second lateral high-voltage MOS transistor, wherein the first doped RESURF regions have an inverse conductivity type with respect to the drift region and the further doped regions have inverse conductivity type as compared to the drain extension region.

Abstract translation: 公开了在基板上形成与所述第一横向高压MOS晶体管和第二横向高压MOS晶体管互补的方法。 根据一个实施例，该方法包括（1）提供第一导电类型的衬底，其包括用于所述第一横向高压MOS晶体管的第一有源区和用于所述第二横向高压MOS晶体管的第二有源区和（2 ）在所述第一有源区中形成所述第一导电类型的至少一个第一掺杂区域，并且在所述第二有源区域中形成从衬底表面延伸到所述衬底内部的所述第二导电类型的漏极延伸区域，所述漏极延伸区域包括同时植入 的掺杂剂通过同一掩模的开口进入第一和第二活性区域。 形成至少一个第一掺杂区域可以是在第一横向高压MOS晶体管中形成双重RESURF结构的优异步骤的子步骤，并且形成双重RESURF结构可以包括形成掺杂的RESURF区域作为两个第一掺杂 区域，其中一个位于第一横向高压MOS晶体管的漂移区以下，其中一个位于第二横向高压MOS晶体管的漏极延伸区之下，其中一个位于第二横向高压MOS晶体管的漏极延伸区之下， 其中所述第一掺杂RESURF区域相对于所述漂移区域具有反向导电类型，并且所述另外的掺杂区域与所述漏极延伸区域相比具有反向导电类型。

公开(公告)号：US20100148255A1

公开(公告)日：2010-06-17

申请号：US12593309

申请日：2008-03-26

Applicant: Felix Fuernhammer ,  Christoph Ellmers ,  Thomas Uhlig ,  Michael Stoisiek

Inventor： Felix Fuernhammer ,  Christoph Ellmers ,  Thomas Uhlig ,  Michael Stoisiek

IPC: H01L29/78 ,  H01L29/06

CPC classification number: H01L29/0634 ,  H01L29/7816 ,  H01L29/7835

Abstract: For achieving an enhanced combination of a low on-resistance at a high break-through voltage a lateral high-voltage MOS transistor comprises a plurality of doped RESURF regions of the first conductivity type within the drift region, wherein the doped RESURF regions are separated from each other by drift region sections in a first lateral direction (y), which is parallel to a substrate surface and is orthogonal to a connecting line from the source region to the drain region, and also in a depth direction, which is orthogonal to the substrate surface, such that in each of said two directions an alternating arrangement of regions of the first and second conductivity types is provided.

Abstract translation: 为了在高突变电压下实现低导通电阻的增强组合，横向高压MOS晶体管包括在漂移区内的第一导电类型的多个掺杂RESURF区域，其中掺杂的RESURF区域与 彼此相对于第一横向方向（y）的漂移区域，其平行于基板表面并且与从源极区域到漏极区域的连接线垂直，并且还与深度方向垂直，该深度方向与 使得在所述两个方向中的每一个中提供所述第一和第二导电类型的区域的交替布置。

公开(公告)号：US20100148276A1

公开(公告)日：2010-06-17

申请号：US12593316

申请日：2008-03-26

Applicant: Thomas Uhlig ,  Felix Fuernhammer ,  Christoph Ellmers

Inventor： Thomas Uhlig ,  Felix Fuernhammer ,  Christoph Ellmers

IPC: H01L27/06 ,  H01L21/8249

CPC classification number: H01L21/8249 ,  H01L27/0623 ,  H01L27/0883

Abstract: The invention relates to a BiMOS semiconductor component having a semiconductor substrate wherein, in a first active region, a depletion-type MOS transistor is formed comprising additional source and drain doping regions of the first conductivity type extending in the downward direction past the depletion region into the body doping region while, in a second active region, (101), a bipolar transistor (100) is formed, the base of which comprises a body doping region (112) and the collector of which comprises a deep pan (110), wherein an emitter doping region (114) of the first conductivity type and a base connection doping region (118) of the second conductivity type are formed in the body doping region. The semiconductor element can be produced with a particularly low process expenditure because it uses the same basic structure for the doping regions in the bipolar transistor as are used in the MOS transistor of the same semiconductor component.

Abstract translation: 本发明涉及一种具有半导体衬底的BiMOS半导体部件，其中在第一有源区中形成耗尽型MOS晶体管，该耗尽型MOS晶体管包括沿向下方向延伸穿过耗尽区的第一导电类型的额外源极和漏极掺杂区域， 在第二有源区中形成（101）双极晶体管（100）的本体掺杂区域，其基极包括体掺杂区域（112），并且其集电极包括深盘（110）， 其中在所述体内掺杂区域中形成有所述第一导电类型的发射极掺杂区域（114）和所述第二导电类型的基极连接掺杂区域（118）。 由于半导体元件对于双相晶体管中的掺杂区域使用相同的基本结构，就像在同一半导体元件的MOS晶体管中使用的那样，可以制造出特别低的工艺成本。