公开(公告)号：US08924452B2

公开(公告)日：2014-12-30

申请号：US13557451

申请日：2012-07-25

申请人： Sheau-Fang Lei ,  Shin-Chi Lai ,  Chuan-An Chang

发明人： Sheau-Fang Lei ,  Shin-Chi Lai ,  Chuan-An Chang

IPC分类号： G06F15/00

CPC分类号： G06F17/141

摘要： A fixed-coefficient variable prime length recursive discrete Fourier transform system includes a pre-processing device, a real-part computation device, an imaginary-part computation device and a post-processing device. The pre-processing device receives N digital input signals and performs order permutation operation to generate first and second temporal signals, wherein N is a prime number. The real-part computation device receives the real part of the first and second temporal signals and performs discrete cosine/sine transform to generate third and fourth temporal signals. The imaginary-part computation device receives the imaginary part of the first and second temporal signals and performs discrete cosine/sine transform to generate fifth and sixth temporal signals. The post-processing device receives the third, fourth, fifth and sixth temporal signals to perform order permutation and addition operations for generating N digital output signals, wherein the N digital output signals are the discrete Fourier transform of the N digital signals.

摘要翻译： 固定系数可变素数长度递归离散傅里叶变换系统包括预处理装置，实部计算装置，虚部计算装置和后处理装置。 预处理装置接收N个数字输入信号并执行顺序置换操作以产生第一和第二时间信号，其中N是素数。 实部计算装置接收第一和第二时间信号的实部，并执行离散余弦/正弦变换以产生第三和第四时间信号。 虚部计算装置接收第一和第二时间信号的虚部，并执行离散余弦/正弦变换以产生第五和第六时间信号。 后处理装置接收第三，第四，第五和第六时间信号以执行用于产生N个数字输出信号的顺序置换和相加操作，其中N个数字输出信号是N个数字信号的离散付里叶变换。

公开(公告)号：US20130173680A1

公开(公告)日：2013-07-04

申请号：US13557451

申请日：2012-07-25

申请人： Sheau Fang LEI ,  Shin Chi LAI ,  Chuan An CHANG

发明人： Sheau Fang LEI ,  Shin Chi LAI ,  Chuan An CHANG

IPC分类号： G06F17/14

CPC分类号： G06F17/141

摘要： A fixed-coefficient variable prime length recursive discrete Fourier transform system includes a pre-processing device, a real-part computation device, an imaginary-part computation device and a post-processing device. The pre-processing device receives N digital input signals and performs order permutation operation to generate first and second temporal signals, wherein N is a prime number. The real-part computation device receives the real part of the first and second temporal signals and performs discrete cosine/sine transform to generate third and fourth temporal signals. The imaginary-part computation device receives the imaginary part of the first and second temporal signals and performs discrete cosine/sine transform to generate fifth and sixth temporal signals. The post-processing device receives the third, fourth, fifth and sixth temporal signals to perform order permutation and addition operations for generating N digital output signals, wherein the N digital output signals are the discrete Fourier transform of the N digital signals.

摘要翻译： 固定系数可变素数长度递归离散傅立叶变换系统包括预处理装置，实部计算装置，虚部计算装置和后处理装置。 预处理装置接收N个数字输入信号并执行顺序置换操作以产生第一和第二时间信号，其中N是素数。 实部计算装置接收第一和第二时间信号的实部，并执行离散余弦/正弦变换以产生第三和第四时间信号。 虚部计算装置接收第一和第二时间信号的虚部，并执行离散余弦/正弦变换以产生第五和第六时间信号。 后处理装置接收第三，第四，第五和第六时间信号以执行用于产生N个数字输出信号的顺序置换和相加操作，其中N个数字输出信号是N个数字信号的离散付里叶变换。