Fringe RLGC model for interconnect parasitic extraction
    1.
    发明申请
    Fringe RLGC model for interconnect parasitic extraction 有权
    用于互连寄生提取的边缘RLGC模型

    公开(公告)号:US20050240883A1

    公开(公告)日:2005-10-27

    申请号:US10829698

    申请日:2004-04-22

    CPC classification number: G06F17/5036

    Abstract: An RLGC library is generated so as to include fringe RLCG functions for 2-D canonical interconnect structures. During parameter extraction for selected interconnect structures of an integrated circuit, printed circuit board, or integrated circuit package design, the RLGC library is used to generate fringe RLGC coefficients which in addition to area RLGC coefficients calculated on-the-fly, are used to generate equivalent RLGC circuits or S-parameters for simulating the interconnect structures.

    Abstract translation: 生成RLGC库,以便包括用于2-D规范互连结构的条纹RLCG功能。 在集成电路,印刷电路板或集成电路封装设计的选定互连结构的参数提取期间,RLGC库用于生成条纹RLGC系数,除了运行中计算的区域RLGC系数之外,还可用于生成 用于模拟互连结构的等效RLGC电路或S参数。

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