公开(公告)号：US5831869A

公开(公告)日：1998-11-03

申请号：US573015

申请日：1995-12-15

申请人： Clive Robert Ellis ,  Robert J. Palermo

发明人： Clive Robert Ellis ,  Robert J. Palermo

IPC分类号： G06F17/50

CPC分类号： G06F17/5045 ,  G06F17/5031

摘要： An automatic process of compacting or "flattening" a hierarchical multi-level logic design for more efficient timing analysis purposes while using electronic design automation tools, the hierarchical multi-level logic design having at least one higher level logic design including at least one instance, but typically a plurality of instances, of a lower level logic design. The process includes creating a file for storing logic design data defining a lower level logic design and timing analysis input data for the lower level logic design, deleting selected logic design data from the file wherein the deleted data represents all internal paths and components of the lower level logic which are not connected to the higher level logic design, thereby leaving only data for external paths and components of the lower level logic design connected to the higher level logic design in the file. The file creation and internal path and component deletion steps are repeated for all lower level logic designs in the overall hierarchical multi-level logic design. Another file is created to hold the logic design data defining the higher level logic design and timing analysis input data for the higher level logic design. The modified logic design data and timing analysis data for the lower level logic designs in the lower level logic design files are automatically substituted into appropriate places in the file for the higher level logic design, thereby decreasing the size of the overall logic design data being processed for timing analysis purposes.

摘要翻译： 在使用电子设计自动化工具的同时，压缩或“扁平化”分级多级逻辑设计以实现更有效的时序分析目的的自动过程，具有至少一个更高级逻辑设计的分级多级逻辑设计包括至少一个实例， 但通常是较低级逻辑设计的多个实例。 该过程包括创建用于存储逻辑设计数据的文件，其定义用于较低级逻辑设计的较低级别逻辑设计和时序分析输入数据，从文件中删除所选择的逻辑设计数据，其中，删除的数据表示所有内部路径和下层 电平逻辑不连接到较高级别的逻辑设计，从而仅留下连接到文件中较高级逻辑设计的较低级别逻辑设计的外部路径和组件的数据。 在整体分层多层次逻辑设计中，对所有较低级逻辑设计重复文件创建和内部路径和组件删除步骤。 创建另一个文件来保存定义更高级逻辑设计和时序分析输入数据的逻辑设计数据，用于较高级逻辑设计。 用于较低级别逻辑设计文件中的较低级别逻辑设计的经修改的逻辑设计数据和时序分析数据被自动替换为用于较高级逻辑设计的文件中的适当位置，从而减小正在处理的整体逻辑设计数据的大小 用于时序分析目的。