公开(公告)号：US06633621B1

公开(公告)日：2003-10-14

申请号：US09531689

申请日：2000-03-20

申请人： Daniel Eric Bishop ,  George Jeffrey Geier ,  Jeffrey Scott Moffett ,  George Arthur Schauer ,  Roger Charles Hart ,  Joel Lloyd Gross

发明人： Daniel Eric Bishop ,  George Jeffrey Geier ,  Jeffrey Scott Moffett ,  George Arthur Schauer ,  Roger Charles Hart ,  Joel Lloyd Gross

IPC分类号： H03D324

CPC分类号： G04G7/00 ,  H03L7/087 ,  H03L7/093

摘要： A system for synchronizing a clock includes a phase-locked loop (PLL) circuit that generates or receives (304) timing errors that are based on timing information from multiple timing sources. Gain blocks (214) weight (306) the timing errors, which are then combined (308) into a loop time error. A loop integrator (226) integrates (310) the loop time error to produce an input used to adjust (312) an oscillator frequency. A corresponding oscillator clock signal is fed back (240) to one or more phase detectors (206), which receive (302) timing reference signals and generate timing errors. When a timing errors indicates that a problem exists with a timing source, the impact of the problematic timing source is reduced (430, 504), or oscillator frequency adjustments are suspended (608). When used on a satellite (700), at least one of the timing errors can be based on times of transmit and times of arrival of time messages exchanged between the satellite and its neighbors (716).

摘要翻译： 用于同步时钟的系统包括基于来自多个定时源的定时信息生成或接收（ 304 ）定时误差的锁相环（PLL）电路。 （ 214 ）权重（ 306 ）定时错误，然后组合（ 308 ）转换为循环时间错误。 循环积分器（ 226 ）将循环时间误差积分（ 310 ）以产生用于调整的输入（ 312 ）振荡器频率。 将相应的振荡器时钟信号反馈（ 240 ）到一个或多个相位检测器（ 206 ）， 302 ）定时参考信号并产生定时误差。 当定时错误表示定时源存在问题时，减少了有问题的定时源的影响（ 430,504 ），或者振荡器频率调整被暂停（< HIL> 608 ）。 当在卫星（ 700 ）上使用时，定时错误中的至少一个可以基于在卫星与其邻居之间交换的时间消息的发送时间和到达时间 （ 716 ）。