公开(公告)号：US06795869B1

公开(公告)日：2004-09-21

申请号：US09794841

申请日：2001-02-27

Applicant: Kenneth S. Morley ,  Todor Cooklev ,  Mark Gray ,  Darrin J. Gibbs

Inventor： Kenneth S. Morley ,  Todor Cooklev ,  Mark Gray ,  Darrin J. Gibbs

IPC: G06F1516

CPC classification number: H04L65/602 ,  H04L29/06027

Abstract: A communication system embodying the invention has a communication channel with at least two ends, one end of the channel being connected to a transmission device with relatively limited computational capacity and an other end of the channel being connected to a computer having relatively large computational capacity. The transmission device includes a signal source node; a set of M−1 delay buffers connected in series and defining a set of M progressively delayed signal nodes, M being a positive integer, one end of the series of M delay buffers being connected to the signal source node; a set of M parallel downsampling operators connected to the M progressively delayed signal nodes; and, a parallel-to-serial converter having M parallel inputs and a single serial output, the M parallel inputs being connected to the outputs of the M parallel downsampling operators and the single serial output being coupled to the one end of the communication channel. A set of M parallel filter coefficient multipliers having respective inputs and outputs and corresponding to the respective coefficients Hi(z−1) of an anti-aliasing filter H(z)=&Sgr;i=0M−1z−iHi(z−M) is implemented in the computer to minimize the computational requirements for the transmission device to simple tasks.

Abstract translation: 体现本发明的通信系统具有至少两端的通信信道，该信道的一端连接到具有相对有限的计算能力的传输设备，并且该信道的另一端连接到具有相对较大计算能力的计算机。 发送装置包括信号源节点; 一组串联连接的M-1个延迟缓冲器，并定义一组M个逐行延迟的信号节点，M为正整数，一系列M个延迟缓冲器的一端连接到信号源节点; 连接到M个逐渐延迟的信号节点的一组M并行下采样算子; 以及具有M个并行输入和单个串行输出的并行 - 串行转换器，所述M个并行输入连接到所述M个并行下采样算子的输出，并且所述单个串行输出耦合到所述通信信道的一端。 具有相应输入和输出并对应于抗混叠滤波器H（z）= Sigmai = 0 z <-i的各个系数Hi（z -1）的一组M并联滤波器系数乘法器 > Hi（z <-M>）在计算机中实现，以最小化传输设备对简单任务的计算要求。

公开(公告)号：USD454125S1

公开(公告)日：2002-03-05

申请号：US29129244

申请日：2000-09-08

Applicant: Gary H. Stout ,  John Marshall ,  Ryan A. Kunz ,  Kenneth S. Morley ,  Darrin J. Gibbs ,  Jeffrey L. Jones

Designer： Gary H. Stout ,  John Marshall ,  Ryan A. Kunz ,  Kenneth S. Morley ,  Darrin J. Gibbs ,  Jeffrey L. Jones

公开(公告)号：US06486810B1

公开(公告)日：2002-11-26

申请号：US09764906

申请日：2001-01-16

Applicant: Todor Cooklev ,  Darrin J. Gibbs ,  Kenneth S. Morley

Inventor： Todor Cooklev ,  Darrin J. Gibbs ,  Kenneth S. Morley

IPC: H03M300

CPC classification number: H03M3/024

Abstract: Continuously variable slope delta modulation coding uses a thresholder having an analog input and a digital output representing the relationship between a signal amplitude at the analog input and a predetermined threshold. An integrator has an output and one input connected to the output of the thresholder and a second input that receives a step size value, the output of the integrator corresponding to a product of the thresholder output and the step size value. An adder has one input that receives an analog input signal that is to be encoded and a second input connected to the output of the integrator. The output of the adder is coupled to the analog input of the thresholder. A step size controller is responsive to an analog signal level related to the analog input signal for varying the step size value in response to variations in the analog signal level.

Abstract translation: 连续可变斜率增量调制编码使用具有模拟输入的阈值器和表示模拟输入端的信号幅度与预定阈值之间的关系的数字输出。 积分器具有连接到阈值器的输出的输出和一个输入，以及接收步长值的第二输入，积分器的输出对应于阈值输出的乘积和步长值。 加法器具有接收要编码的模拟输入信号和连接到积分器的输出的第二输入的一个输入。 加法器的输出耦合到阈值器的模拟输入端。 步长控制器响应于与模拟输入信号相关的模拟信号电平，以响应于模拟信号电平的变化来改变步长值。