公开(公告)号：US5566325A

公开(公告)日：1996-10-15

申请号：US269259

申请日：1994-06-30

申请人： E. William Bruce, II ,  Dave Hartwell ,  David M. Fenwick ,  Denis Foley ,  Stephen R. Van Doren

发明人： E. William Bruce, II ,  Dave Hartwell ,  David M. Fenwick ,  Denis Foley ,  Stephen R. Van Doren

IPC分类号： G11C7/22 ,  G11C8/18 ,  G06F12/00 ,  G06F1/12

CPC分类号： G11C8/18 ,  G11C7/22

摘要： A memory system is provided which can adapt to being coupled to a bus capable of running at different clock speeds. The memory system is responsive to signals provided by a bus speed sensor for modifying the timing of row address strobe (RAS), column address strobe (CAS) and write enable (WE) signals. By modifying the timing of the RAS, CAS, and WE signals, the memory can be operated in systems capable of operating at a variety of bus speeds without suffering latency problems normally associated with changes in bus speed.

摘要翻译： 提供了一种存储器系统，其可以适应于耦合到能够以不同时钟速度运行的总线。 存储器系统响应由总线速度传感器提供的信号，用于修改行地址选通（RAS），列地址选通（CAS）和写使能（WE）信号的定时。 通过修改RAS，CAS和WE信号的时序，可以在能够以各种总线速度工作的系统中操作存储器，而不会遇到通常与总线速度变化相关的延迟问题。

公开(公告)号：US5848258A

公开(公告)日：1998-12-08

申请号：US711387

申请日：1996-09-06

申请人： David M. Fenwick ,  Denis Foley ,  Stephen R. Van Doren ,  Dave Hartwell

发明人： David M. Fenwick ,  Denis Foley ,  Stephen R. Van Doren ,  Dave Hartwell

IPC分类号： G06F12/06 ,  G06F12/02

CPC分类号： G06F12/0607 ,  G06F12/0661

摘要： In accordance with the present invention, an apparatus includes a system bus having memory bank identification signals. Coupled to the system bus are at least two memory modules, each having at least one memory bank, and at least one commander module. The commander module contains decode logic which includes memory mapping registers associated with unique values to be driven on the memory bank identification signals. The memory banks contain compare logic including a virtual node identification register which stores a predetermined value to be compared with the value driven on the memory bank identification signals to determine if the memory bank is the target of the current transaction. Thus, memory banks need not decode the entire system bus address to determine if they are the target of the transaction which reduces the time required to complete a transaction with memory. Further, the apparatus allows memory modules having a different number of memory banks and memory banks capable of storing a different number of addressable locations to be efficiently used in the same computer system.

摘要翻译： 根据本发明，一种装置包括具有存储体识别信号的系统总线。 耦合到系统总线的是至少两个存储器模块，每个存储器模块具有至少一个存储体和至少一个指令器模块。 指挥官模块包含解码逻辑，其包括与要在存储体识别信号上驱动的唯一值相关联的存储器映射寄存器。 存储器组包含比较逻辑，包括虚拟节点识别寄存器，其存储要与存储器组标识信号驱动的值进行比较的预定值，以确定存储体是否为当前事务的目标。 因此，存储器库不需要解码整个系统总线地址，以确定它们是否是事务的目标，这减少了与存储器完成交易所需的时间。 此外，该装置允许具有不同数量的存储体的存储器模块和能够存储不同数量的可寻址位置以在同一计算机系统中有效使用的存储器组。