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36 条记录 (耗时 0.038 秒)

    Method and apparatus for hardware-accelerated encryption/decryption
    1.
    发明授权
    Method and apparatus for hardware-accelerated encryption/decryption 有权
    用于硬件加速加密/解密的方法和装置

    公开(公告)号：US08879727B2

    公开(公告)日：2014-11-04

    申请号：US12201259

    申请日：2008-08-29

    申请人： David E. Taylor ,  Brandon Parks Thurmon ,  Ronald S. Indeck

    发明人： David E. Taylor ,  Brandon Parks Thurmon ,  Ronald S. Indeck

    IPC分类号： H04K1/04 ,  H04L9/00 ,  H04K1/00 ,  H04L9/08 ,  H04L9/06

    CPC分类号： H04L9/0861 ,  H04L9/0618 ,  H04L9/0819 ,  H04L9/0822 ,  H04L9/0844 ,  H04L2209/122 ,  H04L2209/125 ,  H04L2209/24

    摘要： An integrated circuit for data encryption/decryption and secure key management is disclosed. The integrated circuit may be used in conjunction with other integrated circuits, processors, and software to construct a wide variety of secure data processing, storage, and communication systems. A preferred embodiment of the integrated circuit includes a symmetric block cipher that may be scaled to strike a favorable balance among processing throughput and power consumption. The modular architecture also supports multiple encryption modes and key management functions such as one-way cryptographic hash and random number generator functions that leverage the scalable symmetric block cipher. The integrated circuit may also include a key management processor that can be programmed to support a wide variety of asymmetric key cryptography functions for secure key exchange with remote key storage devices and enterprise key management servers. Internal data and key buffers enable the device to re-key encrypted data without exposing data. The key management functions allow the device to function as a cryptographic domain bridge in a federated security architecture.

    摘要翻译： 公开了用于数据加密/解密和安全密钥管理的集成电路。 集成电路可以与其他集成电路，处理器和软件结合使用，以构建各种各样的安全数据处理，存储和通信系统。 集成电路的优选实施例包括对称块密码，其可以被缩放以在处理吞吐量和功耗之间达到良好的平衡。 模块化架构还支持多种加密模式和密钥管理功能，例如利用可扩展对称块密码的单向加密散列和随机数生成器功能。 集成电路还可以包括密钥管理处理器，其可以被编程为支持用于与远程密钥存储设备和企业密钥管理服务器的安全密钥交换的各种不对称密钥密码术功能。 内部数据和密钥缓冲器可使设备重新加密加密数据，而不会暴露数据。 密钥管理功能允许设备在联合安全架构中用作加密域桥。

    Method and System for Low Latency Basket Calculation
    9.
    发明申请
    Method and System for Low Latency Basket Calculation 审中-公开
    低延迟篮计算方法与系统

    公开(公告)号：US20090182683A1

    公开(公告)日：2009-07-16

    申请号：US12013302

    申请日：2008-01-11

    申请人： David E. Taylor ,  Naveen Singla ,  Benjamin C. Brodie ,  Nathaniel Sutton McVicar ,  Justin Ryan Thiel ,  Ronald S. Indeck

    发明人： David E. Taylor ,  Naveen Singla ,  Benjamin C. Brodie ,  Nathaniel Sutton McVicar ,  Justin Ryan Thiel ,  Ronald S. Indeck

    IPC分类号： G06Q40/00 ,  G06F17/40 ,  G06F17/10

    CPC分类号： G06Q40/00 ,  G06Q40/06

    摘要： A basket calculation engine is deployed to receive a stream of data and accelerate the computation of basket values based on that data. In a preferred embodiment, the basket calculation engine is used to process financial market data to compute the net asset values (NAVs) of financial instrument baskets. The basket calculation engine can be deployed on a coprocessor and can also be realized via a pipeline, the pipeline preferably comprising a basket association lookup module and a basket value updating module. The coprocessor is preferably a reconfigurable logic device such as a field programmable gate array (FPGA).

    摘要翻译： 部署篮子计算引擎以接收数据流，并基于该数据加速计算篮值。 在优选实施例中，篮子计算引擎用于处理金融市场数据以计算金融工具篮子的净资产值（NAV）。 篮子计算引擎可以部署在协处理器上，并且也可以通过管道实现，管线优选地包括篮关联查找模块和篮值更新模块。 协处理器优选地是诸如现场可编程门阵列（FPGA）的可重新配置的逻辑器件。

    High speed processing of financial information using FPGA devices
    10.
    发明授权
    High speed processing of financial information using FPGA devices 有权
    使用FPGA器件高速处理财务信息

    公开(公告)号：US08595104B2

    公开(公告)日：2013-11-26

    申请号：US13076951

    申请日：2011-03-31

    申请人： Scott Parsons ,  David E. Taylor ,  David Vincent Schuehler ,  Mark A. Franklin ,  Roger D. Chamberlain

    发明人： Scott Parsons ,  David E. Taylor ,  David Vincent Schuehler ,  Mark A. Franklin ,  Roger D. Chamberlain

    IPC分类号： G06Q40/00

    CPC分类号： G06Q40/04 ,  G06Q40/00 ,  G06Q40/06

    摘要： A high speed apparatus and method for processing a plurality of financial market data messages are disclosed. With respect to an exemplary embodiment, a record memory is employed to store a plurality of records for a plurality of financial instruments, and a reconfigurable logic device is employed to (1) receive financial market data messages, (2) retrieve from the record memory the records for the messages' associated financial instruments, (3) process each received financial market data message to update the record for the financial instrument associated with that message, and wherein each record comprises an interest list that identifies whether any of a plurality of entities have expressed an interest in being notified of data relating to the updated record.

    摘要翻译： 公开了一种用于处理多个金融市场数据消息的高速装置和方法。 对于示例性实施例，使用记录存储器来存储用于多个金融工具的多个记录，并且采用可重构逻辑设备来（1）接收金融市场数据消息，（2）从记录存储器检索 消息相关金融工具的记录，（3）处理每个收到的金融市场数据消息以更新与该消息相关联的金融工具的记录，并且其中每个记录包括识别多个实体中的任何一个的兴趣列表 已表示有兴趣被通知有关更新记录的数据。