公开(公告)号：US07797131B2

公开(公告)日：2010-09-14

申请号：US11844393

申请日：2007-08-24

申请人： Deepak K. Singh ,  Francois Ibrahim Atallah ,  David John Seman

发明人： Deepak K. Singh ,  Francois Ibrahim Atallah ,  David John Seman

IPC分类号： G06F19/00 ,  G06F17/40

CPC分类号： G01R31/31708 ,  G01R31/31725

摘要： A method and circuit are provided for measuring frequency response performance of an integrated circuit by providing a pulse having a rising edge and a falling edge where the pulse is provided to a plurality of serially connected components. The number of these components which have propagated the leading edge of the pulse before the occurrence of the falling edge provide a numeric indication of the circuit's frequency response and performance.

摘要翻译： 提供了一种用于通过提供具有上升沿和下降沿的脉冲来测量集成电路的频率响应性能的方法和电路，其中脉冲被提供给多个串联连接的部件。 在发生下降沿之前传播脉冲前沿的这些部件的数量提供了电路的频率响应和性能的数字指示。

公开(公告)号：US20090055122A1

公开(公告)日：2009-02-26

申请号：US11844393

申请日：2007-08-24

申请人： Deepak K. Singh ,  Francois Ibrahim Atallah ,  David John Seman

发明人： Deepak K. Singh ,  Francois Ibrahim Atallah ,  David John Seman

IPC分类号： G01R31/317

CPC分类号： G01R31/31708 ,  G01R31/31725

摘要： A method and circuit are provided for measuring frequency response performance of an integrated circuit by providing a pulse having a rising edge and a falling edge where the pulse is provided to a plurality of serially connected components. The number of these components which have propagated the leading edge of the pulse before the occurrence of the falling edge provide a numeric indication of the circuit's frequency response and performance.

摘要翻译： 提供了一种用于通过提供具有上升沿和下降沿的脉冲来测量集成电路的频率响应性能的方法和电路，其中脉冲被提供给多个串联连接的部件。 在发生下降沿之前传播脉冲前沿的这些部件的数量提供了电路的频率响应和性能的数字指示。

公开(公告)号：US06330296B1

公开(公告)日：2001-12-11

申请号：US09097130

申请日：1998-06-12

申请人： Francois Ibrahim Atallah ,  George Diniz ,  James Norris Dieffenderfer ,  David John Seman

发明人： Francois Ibrahim Atallah ,  George Diniz ,  James Norris Dieffenderfer ,  David John Seman

IPC分类号： H03D324

CPC分类号： H03L7/0812 ,  H03L7/0891 ,  H03L7/10

摘要： The present invention provides a delay-locked loop (DLL). The DLL comprises a phase-frequency detector (PFD) for receiving a reference signal. The DLL further includes a charge pump which is coupled to the PFD. The DLL also includes a loop filter which is coupled to the charge pump and the PFD. Additionally in the DLL, delay line means is coupled to the charge pump and the loop filter. The delay line means provides a feedback signal to the PFD. The DLL further includes monitor means coupled to the PFD, the charge pump and the loop filter. The monitor means is for detecting when a voltage across the loop filter is at a predetermined level, wherein when the voltage is at the predetermined level the monitor means causes the PFD to enter a pump-down mode until the feedback signal is aligned with the reference signal. An advantage of the present invention is that DLL loop tracking failures based upon a stuck condition are reliably avoided. Specifically, the DLL in accordance with the present invention can reliably recover from the stuck condition in which the adjustable delay is at its lower limit and the PFD asserts the UP control signal. Additionally, the DLL is cost effective and is easily implemented utilizing existing processes.

摘要翻译： 本发明提供一种延迟锁定环（DLL）。 该DLL包括用于接收参考信号的相位频率检测器（PFD）。 该DLL还包括耦合到PFD的电荷泵。 DLL还包括耦合到电荷泵和PFD的环路滤波器。 另外在DLL中，延迟线装置耦合到电荷泵和环路滤波器。 延迟线装置向PFD提供反馈信号。 DLL还包括耦合到PFD的监视器装置，电荷泵和环路滤波器。 监视器装置用于检测环路滤波器两端的电压何时处于预定电平，其中当电压处于预定电平时，监视装置使PFD进入降压模式，直到反馈信号与参考电压对齐 信号。 本发明的优点是可靠地避免了基于卡住状态的DLL循环跟踪故障。 具体地说，根据本发明的DLL可以可靠地从可调延迟处于其下限的停滞状态恢复，PFD断言UP控制信号。 此外，DLL是具有成本效益的，并且可以利用现有的过程容易地实现。

公开(公告)号：US07714635B2

公开(公告)日：2010-05-11

申请号：US11671531

申请日：2007-02-06

申请人： Deepak K. Singh ,  Francois Ibrahim Atallah ,  David John Seman

发明人： Deepak K. Singh ,  Francois Ibrahim Atallah ,  David John Seman

IPC分类号： G05F1/10

CPC分类号： H03K19/00384

摘要： Measurement circuit components are included in an integrated circuit fabricated on a semiconductor substrate. These measurement circuits include registers that are connected to a voltage regulation circuit that provides the integrated circuit voltage source and to a power management circuit. These measurement circuits provide signals to control the voltage regulation circuit for adjusting the voltage output to the integrated circuit based upon a measurement values obtained on the semiconductor device. These measurements include temperature, IR drop at locations on the semiconductor substrate, along with the frequency response of integrated circuit.

摘要翻译： 测量电路元件包括在制造在半导体衬底上的集成电路中。 这些测量电路包括连接到提供集成电路电压源和电源管理电路的电压调节电路的寄存器。 这些测量电路提供信号以控制电压调节电路，用于基于在半导体器件上获得的测量值来调节输出到集成电路的电压。 这些测量包括半导体衬底上的位置处的温度，IR下降以及集成电路的频率响应。

公开(公告)号：US20080186082A1

公开(公告)日：2008-08-07

申请号：US11671531

申请日：2007-02-06

申请人： Deepak K Singh ,  Francois Ibrahim Atallah ,  David John Seman

发明人： Deepak K Singh ,  Francois Ibrahim Atallah ,  David John Seman

IPC分类号： G05F3/02

CPC分类号： H03K19/00384

摘要： Measurement circuit components are included in an integrated circuit fabricated on a semiconductor substrate. These measurement circuits include registers that are connected to a voltage regulation circuit that provides the integrated circuit voltage source and to a power management circuit. These measurement circuits provide signals to control the voltage regulation circuit for adjusting the voltage output to the integrated circuit based upon a measurement values obtained on the semiconductor device. These measurements include temperature, IR drop at locations on the semiconductor substrate, along with the frequency response of integrated circuit.

摘要翻译： 测量电路元件包括在制造在半导体衬底上的集成电路中。 这些测量电路包括连接到提供集成电路电压源和电源管理电路的电压调节电路的寄存器。 这些测量电路提供信号以控制电压调节电路，用于基于在半导体器件上获得的测量值来调节输出到集成电路的电压。 这些测量包括半导体衬底上的位置处的温度，IR下降以及集成电路的频率响应。

公开(公告)号：US06798858B1

公开(公告)日：2004-09-28

申请号：US09497962

申请日：2000-02-04

申请人： Francois Ibrahim Atallah ,  David John Seman

发明人： Francois Ibrahim Atallah ,  David John Seman

IPC分类号： H03D324

CPC分类号： H03L7/085 ,  H03L7/087 ,  H03L7/095 ,  H03L7/10

摘要： The present invention discloses a lock indicator circuit used to indicate a phase lock condition between logic signals. The lock indicator circuit uses a phase detector that generates a pulse width proportional to the phase difference between a reference signal and a feedback signal. Another circuit generates, on each positive edge of the reference and the feedback signals, pulses whose widths are primarily dependent on fixed delay elements. These fixed pulse determine a window in which the pulse from the phase detector will fall as the two signals approach phase lock. Phase lock is signaled by the logic AND of the window pulse and the phase detector pulse. Other circuitry generates a phase lock indication signal if the phase lock signal remains true for a number of consecutive transitions of the reference signal. Likewise a phase unlock indication signal is generated if after phase lock indication, phase unlock occurs and remains for a number of consecutive transitions of the reference signal.

摘要翻译： 本发明公开了一种用于指示逻辑信号之间的锁相状态的锁定指示器电路。 锁定指示器电路使用产生与参考信号和反馈信号之间的相位差成比例的脉冲宽度的相位检测器。 另一个电路在参考的每个正边沿和反馈信号上产生其宽度主要取决于固定延迟元件的脉冲。 这些固定脉冲决定了一个窗口，其中来自相位检测器的脉冲将随着两个信号接近相位锁定而下降。 相位锁定由窗口脉冲和相位检测器脉冲的逻辑“和”发出信号。 如果参考信号的多次连续转换的锁相信号保持为真，则其它电路产生锁相指示信号。 同样地，如果在相位锁定指示，相位解锁发生之后产生相位解锁指示信号，并且在参考信号的多个连续转换中保持相位解锁指示信号。