Memory programming and test circuitry and methods for implementing the
same
    1.
    发明授权
    Memory programming and test circuitry and methods for implementing the same 失效
    存储器编程和测试电路及其实现方法

    公开(公告)号:US5841787A

    公开(公告)日:1998-11-24

    申请号:US975598

    申请日:1997-11-21

    CPC classification number: G01R31/31905

    Abstract: Disclosed is a loadboard that includes a plurality of channel pins that are arranged on the loadboard. The plurality of channel pins are electrically routed on the loadboard to a receptacle that is configured to receive I/O pins of an integrated circuit chip. The loadboard further includes a programming and test circuit that is integrated on the loadboard, and is coupled to a set of the plurality of channel pins to enable communication with the integrated circuit chip. The programming and test circuit includes a programming sub-circuit for communicating a plurality of voltage levels set by a programming vector to the integrated circuit chip, and a bias sub-circuit for communicating a plurality of bias voltage levels set by the programming vector to the integrated circuit chip.

    Abstract translation: 公开了一种装载板,其包括布置在装载板上的多个通道销。 多个通道引脚在负载板上电连接到被配置为接收集成电路芯片的I / O引脚的插座。 装载板还包括集成在装载板上的编程和测试电路,并且耦合到多个通道引脚的一组以使得能够与集成电路芯片进行通信。 编程和测试电路包括用于将由编程矢量设置的多个电压电平传送到集成电路芯片的编程子电路,以及用于将由编程矢量设置的多个偏置电压电平传递给该集成电路芯片的偏置子电路, 集成电路芯片。

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