Combined single-ended and differential signaling interface
    1.
    发明授权
    Combined single-ended and differential signaling interface 有权
    组合单端和差分信号接口

    公开(公告)号:US06836290B1

    公开(公告)日:2004-12-28

    申请号:US09302090

    申请日:1999-04-29

    IPC分类号: H04N314

    CPC分类号: H04N5/335

    摘要: A data interface for CMOS imagers is disclosed that can be either a single-ended interface or a differential interface. The single-ended interface provides compatibility with many existing external devices. Further providing a differential interface allows a lower noise and a lower power interface for external devices that can support a differential signal. The combined single-ended and differential signal interface does not increase the number of pins required for a single-ended only interface. The data transfer width is set to the word width, which allows a fixed timing relationship between the clock edge and data transfer in both single-ended and differential modes. In single-ended mode, the data is transferred once per clock, but in the differential mode, the data is transferred twice per clock, once on each clock edge. This fixed timing relationship eliminates the need for and cost of explicit bit synchronization.

    摘要翻译: 公开了一种用于CMOS成像器的数据接口,其可以是单端接口或差分接口。 单端接口提供与许多现有外部设备的兼容性。 进一步提供差分接口可以为能够支持差分信号的外部设备提供更低的噪声和更低的电源接口。 组合的单端和差分信号接口不会增加单端只接口所需的引脚数。 数据传输宽度设置为字宽,这允许在单端和差模两种方式之间的时钟边沿和数据传输之间的固定时序关系。 在单端模式下,数据每时钟传输一次,但在差分模式下,数据每个时钟传输两次,每个时钟沿一次。 这种固定的时序关系消除了显式位同步的需要和成本。