公开(公告)号：US07719026B2

公开(公告)日：2010-05-18

申请号：US12098546

申请日：2008-04-07

申请人： Lifang Lou ,  Jay R. Chapin ,  Donna Robinson-Hahn

发明人： Lifang Lou ,  Jay R. Chapin ,  Donna Robinson-Hahn

IPC分类号： H01L29/74

CPC分类号： H01L29/87 ,  H01L27/0262

摘要： A protective SCR integrated circuit device is disclosed built on adjacent N and P wells and defining an anode and a cathode. In addition to the anode and cathode contact structures, the device has an n-type stack (N+/ESD) structure bridging the N-Well and the P-Well, and a p-type stack (P+/PLDD) structure in the P-Well. The separation of the n-type stack structure and the p-type stack structure provides a low triggering voltage without involving any external circuitry or terminal, that together with other physical dimensions and processing parameters also provide a relatively high holding voltage without sacrificing the ESD protection robustness. In an embodiment, the triggering voltage may be about 8V while exhibiting a holding voltage, that may be controlled by the lateral dimension of the n-type stack of about 5-7 V.

摘要翻译： 公开了一种保护性SCR集成电路器件，其构造在相邻的N阱和P阱上并且限定阳极和阴极。 除了阳极和阴极接触结构之外，该器件具有桥接N阱和P阱的n型堆叠（N + / ESD）结构，以及P型堆叠（P + / PLDD）结构 -好。 n型堆叠结构和p型堆叠结构的分离提供低触发电压，而不涉及任何外部电路或端子，与其他物理尺寸和处理参数一起提供相对较高的保持电压而不牺牲ESD保护 健壮性 在一个实施例中，触发电压可以为约8V，同时呈现保持电压，其可以由约5-7V的n型叠层的横向尺寸来控制。

公开(公告)号：US20080253046A1

公开(公告)日：2008-10-16

申请号：US12098546

申请日：2008-04-07

申请人： Lifang Lou ,  Jay R. Chapin ,  Donna Robinson-Hahn

发明人： Lifang Lou ,  Jay R. Chapin ,  Donna Robinson-Hahn

IPC分类号： H02H9/00 ,  H01L29/73

CPC分类号： H01L29/87 ,  H01L27/0262

摘要： A protective SCR integrated circuit device is disclosed built on adjacent N and P wells and defining an anode and a cathode. In addition to the anode and cathode contact structures, the device has an n-type stack (N+/ESD) structure bridging the N-Well and the P-Well, and a p-type stack (P+/PLDD) structure in the P-Well. The separation of the n-type stack structure and the p-type stack structure provides a low triggering voltage, that together with other physical dimensions and processing parameters also provide a relatively high holding voltage. In an embodiment, the triggering voltage may be about 8V while exhibiting a holding voltage, that may be controlled by the lateral dimension of the n-type stack of about 5-7 V.

摘要翻译： 公开了一种保护性SCR集成电路器件，其构造在相邻的N阱和P阱上并且限定阳极和阴极。 除了阳极和阴极接触结构之外，该器件具有桥接N阱和P阱的n型堆叠（N + / ESD）结构，以及P型堆叠（P + / PLDD）结构 -好。 n型堆叠结构和p型堆叠结构的分离提供了低触发电压，其与其他物理尺寸和处理参数一起也提供相对较高的保持电压。 在一个实施例中，触发电压可以为约8V，同时呈现保持电压，其可以由约5-7V的n型叠层的横向尺寸来控制。

公开(公告)号：US6101083A

公开(公告)日：2000-08-08

申请号：US215411

申请日：1998-12-18

申请人： Bruce Lloyd Artz ,  Edward P. Eberhardt ,  Kenneth Phillips Moll ,  Donna Robinson-Hahn

发明人： Bruce Lloyd Artz ,  Edward P. Eberhardt ,  Kenneth Phillips Moll ,  Donna Robinson-Hahn

IPC分类号： G01N3/60 ,  H05F3/02

CPC分类号： G01N3/60 ,  H05F3/02

摘要： A method and apparatus for essentially eliminating ESD damage to integrated circuits being subjected to thermal shock testing includes the utilization of a static dissipative plastic carrier capable of withstanding high temperatures (e.g., 155.degree. C.) and exhibiting a surface resistivity in the range of, for example, 10.sup.10 -10.sup.12 .omega./.quadrature.. Such a static dissipative plastic support structure will therefore eliminate static buildup during integrated circuit testing and prevent ESD damage to the circuits.

摘要翻译： 用于基本上消除对受到热冲击测试的集成电路的ESD损害的方法和装置包括利用能够承受高温（例如155℃）并且表现出在以下范围内的表面电阻率的静电耗散塑料载体， 例如，1010-1012 omega /＆squ＆。 因此，这种静电耗散塑料支撑结构将在集成电路测试期间消除静电积累，并防止对电路的ESD损坏。