公开(公告)号：US07689897B2

公开(公告)日：2010-03-30

申请号：US11914700

申请日：2005-05-19

申请人： Michael Priel ,  Eyal Salomon ,  Amir Zatlzman

发明人： Michael Priel ,  Eyal Salomon ,  Amir Zatlzman

IPC分类号： G11B27/00 ,  G06F11/00

CPC分类号： G01R31/318594 ,  G01R31/318552 ,  G01R31/31922

摘要： An integrated circuit and a method for testing an integrated circuit. The method includes providing a first high frequency clock signal sequence to a first group of components of an integrated circuit during a test sequence; characterized by receiving, by a first memory circuit within the integrated circuit, at a low reception rate, a first high frequency signal pattern information and a first low frequency signal pattern information; generating the first high frequency clock signal sequence in response to a first high frequency clock signal and in response to the first high frequency signal pattern information; wherein the first high frequency signal pattern information is being retrieved at a first high retrieval rate from the first memory circuit; and generating a first low frequency clock signal sequence in response a first low frequency clock signal and in response to the first low frequency signal pattern information; wherein the first high frequency signal pattern information is being retrieved at a low retrieval rate from the first memory circuit.

摘要翻译： 集成电路和集成电路测试方法。 该方法包括在测试序列期间向集成电路的第一组分量提供第一高频时钟信号序列; 其特征在于，以集成电路内的第一存储电路以低接收速率接收第一高频信号图案信息和第一低频信号图案信息; 响应于第一高频时钟信号和响应于第一高频信号模式信息产生第一高频时钟信号序列; 其中从所述第一存储器电路以第一高检索率检索所述第一高频信号图案信息; 以及响应于第一低频时钟信号并且响应于所述第一低频信号图案信息产生第一低频时钟信号序列; 其中从所述第一存储器电路以低检索速率检索所述第一高频信号图案信息。

公开(公告)号：US6076096A

公开(公告)日：2000-06-13

申请号：US006212

申请日：1998-01-13

申请人： Eyal Salomon ,  Yoram Salant ,  Oded Norman ,  Vladimir Koifman

发明人： Eyal Salomon ,  Yoram Salant ,  Oded Norman ,  Vladimir Koifman

IPC分类号： G06F7/68

CPC分类号： G06F7/68

摘要： A rate multiplier for rate multiplying a pulse train comprising: an accumulator, a multiplexer for selecting one of a first and a second number of different signs to feed to the accumulator, and a pulse train gate for providing or blocking the pulse train, wherein the multiplexer and the pulse train gate are controlled by the MSB output signal of the accumulator.

摘要翻译： 一种速率乘法器，用于速率乘以脉冲串，包括：累加器，用于选择第一和第二数量的不同符号之一以馈送到累加器的多路复用器，以及用于提供或阻塞脉冲串的脉冲串门，其中 多路复用器和脉冲串门由累加器的MSB输出信号控制。