公开(公告)号：US06362054B1

公开(公告)日：2002-03-26

申请号：US09523782

申请日：2000-03-13

申请人： Seungmoo Choi ,  Donald Thomas Cwynar ,  Scott Francis Shive ,  Timothy Edward Doyle ,  Felix Llevada

发明人： Seungmoo Choi ,  Donald Thomas Cwynar ,  Scott Francis Shive ,  Timothy Edward Doyle ,  Felix Llevada

IPC分类号： H01L21336

CPC分类号： H01L21/266 ,  H01L29/1083

摘要： A halo implant (42, 44) for an MOS transistor (10) is formed in a semiconductor substrate (12) at a shallow implant angle, relative to normal to the substrate surface (29). A polysilicon gate structure (32, 33) is formed over a gate oxide (28) and then a hard mask (70), such as a TEOS-generated layer of silicon oxide, is deposited on an upper surface (68) of the gate. The mask is etched with a blanket anisotropic etch to form a cap-shaped mask (72). The shape of the cap causes the dopant for the halo implant to penetrate to a depth which follows the contour of the cap. Thus, halo implants may be formed which extend under the gate structure without the need for large angle implants and resultant shadowing problems caused by adjacent devices.

公开(公告)号：US06762459B2

公开(公告)日：2004-07-13

申请号：US10038734

申请日：2001-12-31

申请人： Seungmoo Choi ,  Donald Thomas Cwynar ,  Scott Francis Shive ,  Timothy Edward Doyle ,  Felix Llevada

发明人： Seungmoo Choi ,  Donald Thomas Cwynar ,  Scott Francis Shive ,  Timothy Edward Doyle ,  Felix Llevada

IPC分类号： H01L2976

CPC分类号： H01L21/266 ,  H01L29/1083

摘要： A halo implant (42, 44) for an MOS transistor (10) is formed in a semiconductor substrate (12) at a shallow implant angle, relative to normal to the substrate surface (29). A polysilicon gate structure (32, 33) is formed over a gate oxide (28) and then a hard mask (70), such as a TEOS-generated layer of silicon oxide, is deposited on an upper surface (68) of the gate. The mask is etched with a blanket anisotropic etch to form a cap-shaped mask (72). The shape of the cap causes the dopant for the halo implant to penetrate to a depth which follows the contour of the cap. Thus, halo implants may be formed which extend under the gate structure without the need for large angle implants and resultant shadowing problems caused by adjacent devices.

摘要翻译： 在半导体衬底（12）中，相对于衬底表面（29）垂直于浅注入角形成用于MOS晶体管（10）的卤素注入（42,44）。 在栅极氧化物（28）上形成多晶硅栅极结构（32,33），然后在栅极的上表面（68）上沉积诸如TEOS生成的氧化硅层的硬掩模（70） 。 用覆盖层各向异性蚀刻蚀刻掩模以形成帽状掩模（72）。 盖的形状使得晕轮植入物的掺杂剂穿透到遵循盖的轮廓的深度。 因此，可以形成在栅极结构下延伸的晕轮植入物，而不需要大的角度植入物和由相邻的装置引起的由此产生的阴影问题。

公开(公告)号：US06586310B1

公开(公告)日：2003-07-01

申请号：US09384631

申请日：1999-08-27

申请人： Seungmoo Choi ,  Amal M. Hamad ,  Felix Llevada ,  Vivek Saxena ,  Paul Yih

发明人： Seungmoo Choi ,  Amal M. Hamad ,  Felix Llevada ,  Vivek Saxena ,  Paul Yih

IPC分类号： H01L2702

CPC分类号： H01L27/11 ,  H01L27/1112

摘要： The present invention provides a method of manufacturing a resistor for use in a memory element and a semiconductor device employing the resistor. The method of manufacturing may comprise forming a dielectric layer over an active region of a semiconductor wafer and forming a resistive layer on the dielectric layer. The resistive layer comprises a compound wherein a first element of the compound is a Group III or Group IV element and a second element of the compound is a Group IV or Group V element. The method further comprises connecting an electrical interconnect structure to the resistive layer that electrically connects the resistive layer to the active region.

摘要翻译： 本发明提供一种制造用于存储元件的电阻器和采用该电阻器的半导体器件的方法。 制造方法可以包括在半导体晶片的有源区上形成电介质层，并在电介质层上形成电阻层。 电阻层包括化合物，其中化合物的第一元素是III族或IV族元素，该化合物的第二元素是IV族或V族元素。 该方法还包括将电互连结构连接到将电阻层电连接到有源区的电阻层。