Extended page mode with memory address translation using a linear shift
register
    1.
    发明授权
    Extended page mode with memory address translation using a linear shift register 失效
    使用线性移位寄存器的存储器地址转换的扩展页模式

    公开(公告)号:US6148388A

    公开(公告)日:2000-11-14

    申请号:US007621

    申请日:1998-01-15

    IPC分类号: G06F12/02 G11C8/04 G06F12/06

    CPC分类号: G11C8/04 G06F12/0207

    摘要: The present disclosure concerns a method and apparatus for accessing a memory device, such as a dynamic random access memory (DRAM). The DRAM has a plurality of rows, wherein each row has a plurality of DRAM paragraphs comprised of a plurality of contiguous columns. A linear shift register (LSR) translates a plurality of logical addresses to corresponding physical address locations in the DRAM. Each translated physical address is comprised of a row address and a column address. A physical address, including the row and column addresses, is accessed from the LSR. To access the DRAM paragraph at the accessed physical address, the row in the DRAM at the accessed row address location is strobed to setup and precharge the row. Following, all columns in the DRAM paragraph at the accessed physical address are strobed. After strobing the columns in a DRAM paragraph, the next physical address in the LSR, including the next row and column addresses, is accessed. The row in the DRAM at the next accessed row address is strobed to setup and precharge the row upon determining that the next row address is different than the previously accessed row address. Regardless of whether the next accessed row address is strobed or whether the previous precharge and setup is maintained, all columns in the DRAM paragraph at the accessed physical address are strobed.

    摘要翻译: 本公开涉及用于访问诸如动态随机存取存储器(DRAM)的存储器件的方法和装置。 DRAM具有多行,其中每行具有由多个连续列组成的多个DRAM段落。 线性移位寄存器(LSR)将多个逻辑地址转换为DRAM中相应的物理地址位置。 每个翻译的物理地址由行地址和列地址组成。 从LSR访问包括行和列地址的物理地址。 要访问所访问的物理地址的DRAM段落,在所访问的行地址位置的DRAM中的行被选通以建立和预充行。 接下来,选通所访问物理地址的DRAM段中的所有列。 选择DRAM段落中的列后,可以访问LSR中的下一个物理地址,包括下一行和列地址。 在下一个访问的行地址的DRAM中的行被选通以在确定下一行地址不同于先前访问的行地址时建立和预充行。 无论下一个访问的行地址是否选通,或者是否保持先前的预充电和设置,都会选通所访问的物理地址的DRAM段落中的所有列。

    Extended page mode with a skipped logical addressing for an embedded
longitudinal redundancy check scheme
    2.
    发明授权
    Extended page mode with a skipped logical addressing for an embedded longitudinal redundancy check scheme 失效
    扩展页面模式,用于嵌入式纵向冗余校验方案的跳过逻辑寻址

    公开(公告)号:US6021482A

    公开(公告)日:2000-02-01

    申请号:US007618

    申请日:1998-01-15

    IPC分类号: G06F11/10 G06F12/02 G06F12/00

    CPC分类号: G06F11/1008 G06F12/02

    摘要: The present disclosure concerns a method and apparatus for mapping each of a plurality of logical addresses to a physical address identifying a location in a memory device. The memory device has a plurality of columns and rows, wherein each row has a plurality of data paragraphs including data and at least one parity paragraph including parity data. Each paragraph is comprised of a plurality of contiguous columns. A physical address identifies a location of a paragraph in the memory device. To map the logical addresses to physical addresses, a determination must be made as to whether the row and column portions of each logical address identify a physical address location including parity data. If a logical address identifies a physical address location in the memory device including parity data, then the logical address is incremented until the row and column portions of the logical address identify a physical address location not including parity data. The mapping is then conducted by setting the column and row portions of the physical address to the column and row portions of one of the: (i) logical address upon determining that the logical address does not identify a physical address location including parity data and (ii) the incremented logical address upon determining that the logical address identifies a physical address location including parity data.

    摘要翻译: 本公开涉及用于将多个逻辑地址中的每一个映射到识别存储器设备中的位置的物理地址的方法和装置。 存储器件具有多个列和行,其中每行具有包括数据的多个数据段落和包括奇偶校验数据的至少一个奇偶校验段。 每个段落由多个连续的列组成。 物理地址标识存储设备中段落的位置。 为了将逻辑地址映射到物理地址,必须确定每个逻辑地址的行和列部分是否识别包括奇偶校验数据的物理地址位置。 如果逻辑地址识别包括奇偶校验数据的存储设备中的物理地址位置,则逻辑地址增加,直到逻辑地址的行和列部分标识不包括奇偶校验数据的物理地址位置。 然后通过在确定逻辑地址不识别包括奇偶校验数据的物理地址位置的情况下,将物理地址的列和行部分设置为以下之一的列和行部分来执行映射:(i)逻辑地址; ii)在确定逻辑地址标识包括奇偶校验数据的物理地址位置时增加的逻辑地址。