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公开(公告)号：US4648077A
公开(公告)日：1987-03-03
申请号：US693422
申请日：1985-01-22
CPC分类号： G11C7/1006 , G11C7/1075 , G09G2360/123
摘要： A semiconductor memory circuit includes memory arrays (10), (12), (14) and (16). Each of the memory arrays has associated therewith shift registers (34), (36), (38) and (40). Transfer gates (54) are disposed between the memory arrays and the associated shift registers. A control circuit (69) is provided for receiving an external transfer signal and transferring the data between the arrays and the associated shift registers. The shift registers are clocked in response to receiving an external shift clock signal to serially output data therefrom. A delay circuit (292) is provided for delaying shifting of data for a predetermined duration to ensure that a complete transfer of data has been effected. Transfer of data is inhibited until the occurrence of the XBOOT signal by circuit (296) to provide for early occurrence of the transfer signal. Data access is maintained by a delay circuit (330) to accommodate late occurrence of the transfer signal by delaying the internal row address strobe.
摘要翻译： 半导体存储器电路包括存储器阵列（10），（12），（14）和（16）。 每个存储器阵列都具有移位寄存器（34），（36），（38）和（40）。 传输门（54）设置在存储器阵列和相关联的移位寄存器之间。 提供控制电路（69）用于接收外部传送信号并在阵列和相关联的移位寄存器之间传送数据。 响应于接收到外部移位时钟信号来对移位寄存器进行时钟输出以从其中串行输出数据。 提供延迟电路（292），用于延迟数据在预定持续时间内的移位，以确保数据的完整传送已经实现。 数据传输被禁止，直到由电路（296）发生XBOOT信号以提供传输信号的早期发生。 延迟电路（330）维持数据访问，以通过延迟内部行地址选通来适应传输信号的晚期发生。
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公开(公告)号：US4667313A
公开(公告)日：1987-05-19
申请号：US693424
申请日：1985-01-22
CPC分类号： G11C7/1075 , G11C7/1006 , G09G2360/123
摘要： A semiconductor memory comprises four arrays (10), (12), (14) and (16) disposed on a single semiconductor chip. Each of the arrays has a serial shift register (86) associated therewith. Data is transferred from the bit lines of the associated array through a transfer gate (90) for storage in the shift register (86). A tap latch (88) is provided on the output of each of the shift bits in the shift register (86) for determining the output therefrom. The tap latch (88) stores a tap decode signal which is decoded from a tap address by the column decoder (30). The column decoder (30) also decodes the column address in the random mode. The tap decode signal selects any of the shift bits in the shift register (86).
摘要翻译： 半导体存储器包括设置在单个半导体芯片上的四个阵列（10），（12），（14）和（16）。 每个阵列具有与其相关联的串行移位寄存器（86）。 数据通过传输门（90）从相关阵列的位线传输，以便存储在移位寄存器（86）中。 在移位寄存器（86）中的每个移位位的输出上提供抽头锁存器（88），用于确定其输出。 抽头锁存器（88）存储由列解码器（30）从抽头地址解码的抽头解码信号。 列解码器（30）还以随机模式对列地址进行解码。 抽头解码信号选择移位寄存器（86）中的任何移位位。
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