公开(公告)号：US5760484A

公开(公告)日：1998-06-02

申请号：US798560

申请日：1997-02-11

申请人： Chang-Hsun Lee ,  Fu-Cheng Lin ,  Chen-Tai Kuo

发明人： Chang-Hsun Lee ,  Fu-Cheng Lin ,  Chen-Tai Kuo

IPC分类号： G03F9/00 ,  H01L23/544

CPC分类号： G03F9/70 ,  H01L23/544 ,  H01L2223/5442 ,  H01L2223/54426 ,  H01L2223/54453 ,  H01L2223/5446 ,  H01L2924/0002

摘要： An alignment mark for increasing the accuracy of an alignment includes a cross pattern, two horizontal line patterns having serrated shape. The cross pattern is typically formed over a scribe line for alignment in semiconductor process. The cross pattern includes a vertical line and a horizontal line. The vertical line is vertical to the scribe line while the horizontal line is parallel to the scribe line. The horizontal patterns which are parallel to the scribe line are respectively connected to one end of the vertical line. The horizontal patterns have serrated patterns which are used to change the shape of a noise signal. The high of the serrated shape pattern is about 3 micro meters while the width of the serrated shape pattern is about 3 micro meters.

摘要翻译： 用于提高对准精度的对准标记包括交叉图案，具有锯齿形状的两个水平线图案。 交叉图案通常形成在划线上以用于半导体工艺中的对准。 交叉图案包括垂直线和水平线。 垂直线垂直于划线，而水平线平行于划线。 平行于划线的水平图案分别连接到垂直线的一端。 水平图案具有用于改变噪声信号形状的锯齿图案。 锯齿状形状图案的高度为约3微米，而锯齿形状图案的宽度为约3微米。

公开(公告)号：US06492263B1

公开(公告)日：2002-12-10

申请号：US09684038

申请日：2000-10-06

申请人： Hsin-Tang Peng ,  Fu-Cheng Lin ,  Chun-Wei Chen

发明人： Hsin-Tang Peng ,  Fu-Cheng Lin ,  Chun-Wei Chen

IPC分类号： H01L2144

CPC分类号： H01L21/76831 ,  H01L21/76807 ,  H01L21/76808 ,  H01L21/7681 ,  H01L2221/1031

摘要： Disclosed is a dual damascene process for a semiconductor device with two low dielectric constant layers in a stack thereof, in which a via hole and a trench connecting with the via hole are formed respectively in the dielectric layers and a conductor is filled in the via hole and the trench to connect with a conductive region below the via hole after a barrier layer between the via hole and the conductive region is removed. A liner is deposited on the sidewalls of the dielectric layers in the via hole and the trench before the removal of the barrier layer to prevent particles of the conductive region such as copper from sputtering up to the dielectric layers when removing the barrier layer. An etch-stop layer inserted between the dielectric layers is pulled back to be spaced from the via hole with a distance to improve the trench-to-via alignment.

摘要翻译： 公开了一种在其叠层中具有两个低介电常数层的半导体器件的双镶嵌工艺，其中通孔和与通孔连接的沟槽分别形成在电介质层中，并且导体填充在通孔中 并且在通孔和导电区域之间的阻挡层被去除之后，沟槽与通孔之下的导电区域连接。 在去除阻挡层之前，衬垫沉积在通孔和沟槽中的电介质层的侧壁上，以在去除阻挡层时防止诸如铜的导电区域的颗粒溅射到电介质层。 插入电介质层之间的蚀刻停止层被拉回以与通孔间隔开一定距离，以改善沟槽到通孔对准。