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公开(公告)号:US20230144556A1
公开(公告)日:2023-05-11
申请号:US17917643
申请日:2020-05-25
Applicant: INSTITUTE OF AUTOMATION, CHINESE ACADEMY OF SCIENCES , GUANGDONG INSTITUTE OF ARTIFICIAL INTELLIGENCE AND ADVANCED COMPUTING
Inventor: Lingtian ZHAO , Jie HAO , Jun LIANG , Yafang SONG , Lin SHU , Sai MA , Qiuxiang FAN , Hui FENG
CPC classification number: G06F30/34 , G06F17/142 , G06F7/4876
Abstract: Disclosed in the present disclosure is an FPGA implementation device and method for an FBLMS algorithm based on block floating point. The method includes: blocking, caching, and reassembling a reference signal, by an input caching and converting module, converting into a block floating point system and performing FFT; filtering, by a filtering module, in a frequency domain and performing dynamic truncation; caching, by an error calculating and output caching module, a target signal on a block basis, converting into a block floating point system, subtracting an output result output from the filtering module from the converted target signal to obtain an error signal, converting the error signal into a fixed point system to obtain a final cancellation result; obtaining, by a weight adjustment amount calculating module and a weight updating and storing module, an adjustment amount of a frequency domain block weight and updating the frequency domain block weight.
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公开(公告)号:US20230086756A1
公开(公告)日:2023-03-23
申请号:US17597984
申请日:2020-05-25
Applicant: Institute of Automation, Chinese Academy of Sciences , Guangdong Institute of Artificial Intelligence and Advanced Computing
Inventor: Zhifeng Lv , Jie Hao , Jun Liang , Lin Shu , Meiting Zhao , Yafang Song , Qiuxiang Fan
IPC: G06F9/50
Abstract: The field of high-speed data acquisition and network data processing, and particularly relates to an Ethernet data stream recording method, an Ethernet data stream recording system, and an Ethernet data stream recording device for a high-speed data acquisition system. It is intended to solve problems such as a low utilization rate of CPU, poor system compatibility, difficulty in packaging and deployment and low reliability of system transmission of the traditional high-speed data acquisition system. The method of the present disclosure includes: isolating a preset number of CPU cores after a Linux operating system is booted; uninstalling a kernel network card driver of the operating system and creating a hugepage memory pool; for each 10-gigabit network card, allocating a corresponding data-receiving buffer pool and a corresponding lock-free FIFO buffer, and initializing a PCIE register of each 10 gigabit network card such that each 10-gigabit network card enters into an acquisition state; and continuously receiving packets acquired by each 10 gigabit network card in a driving manner of user space polling and performing disk recording. According to the present disclosure, the utilization rate of CPU, system compatibility and transmission reliability are improved and the difficulty in packaging and deployment is decreased.
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公开(公告)号:US11941449B2
公开(公告)日:2024-03-26
申请号:US17597984
申请日:2020-05-25
Applicant: Institute of Automation, Chinese Academy of Sciences , Guangdong Institute of Artificial Intelligence and Advanced Computing
Inventor: Zhifeng Lv , Jie Hao , Jun Liang , Lin Shu , Meiting Zhao , Yafang Song , Qiuxiang Fan
CPC classification number: G06F9/5027 , G06F9/5016
Abstract: The field of high-speed data acquisition and network data processing, and particularly relates to an Ethernet data stream recording method, an Ethernet data stream recording system, and an Ethernet data stream recording device for a high-speed data acquisition system. It is intended to solve problems such as a low utilization rate of CPU, poor system compatibility, difficulty in packaging and deployment and low reliability of system transmission of the traditional high-speed data acquisition system. The method of the present disclosure includes: isolating a preset number of CPU cores after a Linux operating system is booted; uninstalling a kernel network card driver of the operating system and creating a hugepage memory pool; for each 10-gigabit network card, allocating a corresponding data-receiving buffer pool and a corresponding lock-free FIFO buffer, and initializing a PCIE register of each 10-gigabit network card such that each 10-gigabit network card enters into an acquisition state; and continuously receiving packets acquired by each 10-gigabit network card in a driving manner of user space polling and performing disk recording. According to the present disclosure, the utilization rate of CPU, system compatibility and transmission reliability are improved and the difficulty in packaging and deployment is decreased.
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