公开(公告)号：US08589854B2

公开(公告)日：2013-11-19

申请号：US12835628

申请日：2010-07-13

申请人： Pius Ng ,  Satish Padmanabhan ,  Anand Pandurangan ,  Ananth Durbha ,  Suresh Kadiyala ,  Gary Oblock

发明人： Pius Ng ,  Satish Padmanabhan ,  Anand Pandurangan ,  Ananth Durbha ,  Suresh Kadiyala ,  Gary Oblock

IPC分类号： G06F11/22

CPC分类号： G06F17/505 ,  G06F2217/78

摘要： Systems and methods are disclosed to manage power in a custom integrated circuit (IC) design by receiving a specification of the custom integrated circuit including computer readable code and generating a profile of the computer readable code to determine instruction usage; automatically generating a processor architecture uniquely customized to the computer readable code, the processor architecture having one or more processing blocks and one or more power domains; determining when each processing block is needed based on the code profile and assigning each block to one of the power domains; and gating the power domains with power based on the code profile; and synthesizing the generated architecture into a computer readable description of the custom integrated circuit for semiconductor fabrication.

摘要翻译： 公开了通过接收包括计算机可读代码的定制集成电路的规范并生成计算机可读代码的简档以确定指令使用的方式来管理定制集成电路（IC）设计中的电力的系统和方法; 自动生成针对所述计算机可读代码唯一定制的处理器架构，所述处理器架构具有一个或多个处理块和一个或多个电源域; 基于所述代码简档来确定每个处理块是否需要;以及将每个块分配给所述功率域中的一个; 并根据代码简档对功率域进行选通; 以及将生成的架构合成到用于半导体制造的定制集成电路的计算机可读描述中。

公开(公告)号：US08185862B2

公开(公告)日：2012-05-22

申请号：US12835640

申请日：2010-07-13

申请人： Ananth Durbha ,  Pius Ng ,  Gary Oblock ,  Suresh Kadiyala ,  Satish Padmanabhan

发明人： Ananth Durbha ,  Pius Ng ,  Gary Oblock ,  Suresh Kadiyala ,  Satish Padmanabhan

IPC分类号： G06F9/455 ,  G06F17/50

CPC分类号： G06F17/5068 ,  G06F17/5045

摘要： Systems and methods are disclosed to automatically synthesize a custom integrated circuit by receiving a specification of the custom integrated circuit including computer readable code and generating a profile of the computer readable code to determine instruction usage; automatically generating a processor architecture uniquely customized to the computer readable code, the processor architecture having one or more processing blocks to implement one or more instructions; determining an instruction execution sequence based on the code profile and reassigning the instruction sequence to spread operation to different blocks on the IC to reduce hot spots; and synthesizing the generated processor chip specification into a computer readable description of the custom integrated circuit for semiconductor fabrication.

摘要翻译： 公开了通过接收包括计算机可读代码的定制集成电路的规范并生成计算机可读代码的简档以确定指令使用来自动合成定制集成电路的系统和方法; 自动生成针对所述计算机可读代码独特定制的处理器架构，所述处理器架构具有一个或多个处理块以实现一个或多个指令; 基于代码简档确定指令执行序列，并重新分配指令序列以将操作扩展到IC上的不同块以减少热点; 并将生成的处理器芯片规范合成到用于半导体制造的定制集成电路的计算机可读描述中。

公开(公告)号：US20120017189A1

公开(公告)日：2012-01-19

申请号：US12835640

申请日：2010-07-13

申请人： Ananth Durbha ,  Pius Ng ,  Gary Oblock ,  Suresh Kadiyala ,  Satish Padmanabhan

发明人： Ananth Durbha ,  Pius Ng ,  Gary Oblock ,  Suresh Kadiyala ,  Satish Padmanabhan

IPC分类号： G06F17/50 ,  G06F9/44

CPC分类号： G06F17/5068 ,  G06F17/5045

摘要： Systems and methods are disclosed to automatically synthesize a custom integrated circuit by receiving a specification of the custom integrated circuit including computer readable code and generating a profile of the computer readable code to determine instruction usage; automatically generating a processor architecture uniquely customized to the computer readable code, the processor architecture having one or more processing blocks to implement one or more instructions; determining an instruction execution sequence based on the code profile and reassigning the instruction sequence to spread operation to different blocks on the IC to reduce hot spots; and synthesizing the generated processor chip specification into a computer readable description of the custom integrated circuit for semiconductor fabrication.

摘要翻译： 公开了通过接收包括计算机可读代码的定制集成电路的规范并生成计算机可读代码的简档以确定指令使用来自动合成定制集成电路的系统和方法; 自动生成针对所述计算机可读代码独特定制的处理器架构，所述处理器架构具有一个或多个处理块以实现一个或多个指令; 基于代码简档确定指令执行序列，并重新分配指令序列以将操作扩展到IC上的不同块以减少热点; 并将生成的处理器芯片规范合成到用于半导体制造的定制集成电路的计算机可读描述中。

公开(公告)号：US08561005B2

公开(公告)日：2013-10-15

申请号：US13452891

申请日：2012-04-22

申请人： Ananth Durbha ,  Pius Ng ,  Gary Oblock ,  Suresh Kadiyala ,  Satish Padmanabhan

发明人： Ananth Durbha ,  Pius Ng ,  Gary Oblock ,  Suresh Kadiyala ,  Satish Padmanabhan

IPC分类号： G06F9/455 ,  G06F17/50

CPC分类号： G06F17/5068 ,  G06F17/5045

摘要： Systems and methods are disclosed to automatically synthesize a custom integrated circuit by automatically generating an application specific instruction set processor architecture uniquely customized to the computer readable code with a compiler-in-the-loop to compile, assemble and link code for each processor architecture iteration, the processor architecture having one or more processing blocks on the IC executing one or more instructions; and synthesizing the generated architecture into a computer readable description of the custom integrated circuit for semiconductor fabrication.

摘要翻译： 系统和方法被公开以通过自动地生成针对每个处理器架构迭代来编译，组合和链接代码的编译器在循环中独特地定制到计算机可读代码的应用特定指令集处理器架构来自动合成定制集成电路 所述处理器架构在所述IC上具有执行一个或多个指令的一个或多个处理块; 以及将生成的架构合成到用于半导体制造的定制集成电路的计算机可读描述中。

公开(公告)号：US5943691A

公开(公告)日：1999-08-24

申请号：US579435

申请日：1995-12-27

申请人： David R. Wallace ,  Gary Oblock

发明人： David R. Wallace ,  Gary Oblock

IPC分类号： G06F9/45 ,  G06F12/08 ,  G06F11/00

CPC分类号： G06F8/4442 ,  G06F12/0864

摘要： A method and apparatus is provided for determining and resolving cache conflicts among data arrays that are stored in the main memory of a computer system in which the main memory is coupled with a memory cache that is coupled in turn with a microprocessor. According to the method of the invention, a cache shape vector that characterizes the size and dimension of the cache is determined under computer control. A determination of at least one cache conflict among the arrays stored in the main memory is then determined, in addition to the conflict region in the cache for the conflicting arrays. A padding value is then determined for the arrays stored in the main memory, and the memory locations of the arrays are adjusted in accordance with the padding value to prevent cache conflicts when the data from the conflicting arrays is transferred from the main memory into the cache.

摘要翻译： 提供了一种用于确定和解决存储在计算机系统的主存储器中的数据阵列之间的高速缓存冲突的方法和装置，其中主存储器与依次与微处理器耦合的存储器高速缓存耦合。 根据本发明的方法，在计算机控制下确定表征高速缓存的大小和尺寸的高速缓存形状向量。 此外，除了冲突阵列的缓存中的冲突区域之外，还确定存储在主存储器中的阵列之间的至少一个高速缓存冲突的确定。 然后，为存储在主存储器中的阵列确定填充值，并且根据填充值来调整阵列的存储器位置，以防止冲突阵列的数据从主存储器传输到高速缓存器时发生高速缓存冲突 。

公开(公告)号：US08572544B2

公开(公告)日：2013-10-29

申请号：US13452893

申请日：2012-04-22

申请人： Ananth Durbha ,  Pius Ng ,  Gary Oblock ,  Suresh Kadiyala ,  Satish Padmanabhan

发明人： Ananth Durbha ,  Pius Ng ,  Gary Oblock ,  Suresh Kadiyala ,  Satish Padmanabhan

IPC分类号： G06F17/50 ,  G06F9/455

CPC分类号： G06F17/5068 ,  G06F17/5045

摘要： Systems and methods are disclosed to automatically method to manage power in a custom integrated circuit (IC) design with a code profile by receiving an instruction execution sequence based on the code profile and reassigning or delaying the instruction sequence to spread operations or activities over a plurality of processing blocks to reduce hot spots; applying sub-region weight distributions to estimate power hot-spot locations; and synthesizing the generated architecture into a computer readable description of the custom integrated circuit for semiconductor fabrication.

摘要翻译： 公开了系统和方法以通过基于代码简档接收指令执行序列并重新分配或延迟指令序列来扩展多个操作或活动来自动地通过代码简档来管理定制集成电路（IC）设计中的电力的方法 的加工块来减少热点; 应用子区域权重分布来估计功率热点位置; 以及将生成的架构合成到用于半导体制造的定制集成电路的计算机可读描述中。

公开(公告)号：US20130111426A1

公开(公告)日：2013-05-02

申请号：US13452891

申请日：2012-04-22

申请人： Ananth Durbha ,  Pius Ng ,  Gary Oblock ,  Suresh Kadiyala ,  Satish Padmanabhan

发明人： Ananth Durbha ,  Pius Ng ,  Gary Oblock ,  Suresh Kadiyala ,  Satish Padmanabhan

IPC分类号： G06F17/50

CPC分类号： G06F17/5068 ,  G06F17/5045

摘要： Systems and methods are disclosed to automatically synthesize a custom integrated circuit by automatically generating an application specific instruction set processor architecture uniquely customized to the computer readable code with a compiler-in-the-loop to compile, assemble and link code for each processor architecture iteration, the processor architecture having one or more processing blocks on the IC executing one or more instructions; and synthesizing the generated architecture into a computer readable description of the custom integrated circuit for semiconductor fabrication.

摘要翻译： 系统和方法被公开以通过自动地生成针对每个处理器架构迭代来编译，组合和链接代码的编译器在循环中独特地定制到计算机可读代码的应用特定指令集处理器架构来自动合成定制集成电路 所述处理器架构在所述IC上具有执行一个或多个指令的一个或多个处理块; 以及将生成的架构合成到用于半导体制造的定制集成电路的计算机可读描述中。

公开(公告)号：US20130104097A1

公开(公告)日：2013-04-25

申请号：US13452893

申请日：2012-04-22

申请人： Ananth Durbha ,  Pius Ng ,  Gary Oblock ,  Suresh Kadiyala ,  Satish Padmanabhan

发明人： Ananth Durbha ,  Pius Ng ,  Gary Oblock ,  Suresh Kadiyala ,  Satish Padmanabhan

IPC分类号： G06F17/50

CPC分类号： G06F17/5068 ,  G06F17/5045

摘要： Systems and methods are disclosed to automatically method to manage power in a custom integrated circuit (IC) design with a code profile by receiving an instruction execution sequence based on the code profile and reassigning or delaying the instruction sequence to spread operations or activities over a plurality of processing blocks to reduce hot spots; applying sub-region weight distributions to estimate power hot-spot locations; and synthesizing the generated architecture into a computer readable description of the custom integrated circuit for semiconductor fabrication.

摘要翻译： 公开了系统和方法以通过基于代码简档接收指令执行序列并重新分配或延迟指令序列来扩展多个操作或活动来自动地通过代码简档来管理定制集成电路（IC）设计中的电力的方法 的加工块来减少热点; 应用子区域权重分布来估计功率热点位置; 以及将生成的架构合成到用于半导体制造的定制集成电路的计算机可读描述中。

公开(公告)号：US20120017198A1

公开(公告)日：2012-01-19

申请号：US12835628

申请日：2010-07-13

申请人： Pius Ng ,  Satish Padmanabhan ,  Anand Pandurangan ,  Ananth Durbha ,  Suresh Kadiyala ,  Gary Oblock

发明人： Pius Ng ,  Satish Padmanabhan ,  Anand Pandurangan ,  Ananth Durbha ,  Suresh Kadiyala ,  Gary Oblock

IPC分类号： G06F9/44 ,  G06F17/50

CPC分类号： G06F17/505 ,  G06F2217/78

摘要： Systems and methods are disclosed to manage power in a custom integrated circuit (IC) design by receiving a specification of the custom integrated circuit including computer readable code and generating a profile of the computer readable code to determine instruction usage; automatically generating a processor architecture uniquely customized to the computer readable code, the processor architecture having one or more processing blocks and one or more power domains; determining when each processing block is needed based on the code profile and assigning each block to one of the power domains; and gating the power domains with power based on the code profile; and synthesizing the generated architecture into a computer readable description of the custom integrated circuit for semiconductor fabrication.

摘要翻译： 公开了通过接收包括计算机可读代码的定制集成电路的规范并生成计算机可读代码的简档以确定指令使用的方式来管理定制集成电路（IC）设计中的电力的系统和方法; 自动生成针对所述计算机可读代码唯一定制的处理器架构，所述处理器架构具有一个或多个处理块和一个或多个电源域; 基于所述代码简档来确定每个处理块是否需要;以及将每个块分配给所述功率域中的一个; 并根据代码简档对功率域进行选通; 以及将生成的架构合成到用于半导体制造的定制集成电路的计算机可读描述中。