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    Phase locked loop with bandwidth ramp
    2.
    发明授权
    Phase locked loop with bandwidth ramp 失效
    具有带宽斜坡的锁相环

    公开(公告)号：US4954788A

    公开(公告)日：1990-09-04

    申请号：US453356

    申请日：1989-12-18

    申请人： Michael Leis ,  Gary S. Engelson ,  Bruce J. Lawrence

    发明人： Michael Leis ,  Gary S. Engelson ,  Bruce J. Lawrence

    IPC分类号： H03L7/089 ,  H03L7/107

    CPC分类号： H03L7/107 ,  H03L7/0898

    摘要： A phase locked loop that operates on an input signal received from a disk drive and similar data processing system peripherals, where the input signal has a preamble portion and a data portion. The phase locked loop providing a digital clock signal which is phase locked to the preamble portion. This is accomplished by adjusting the loop response time so that it monotonically decreases in amplitude beginning at a time when the phase locked loop receives the preamble portion and continuing to monotonically decrease during at least a portion of the time that the phase locked loop receives the data portion. The response time may be monotonically decreased in any suitable fashion, such as linearly or exponentially. A specific embodiment of a linearly decreasing signal generator used with a charge pump is disclosed. The results of computer simulations showing a decrease in lock acquisition time and increased noise immunity with shortened preamble time are also discussed.

    摘要翻译： 对从盘驱动器接收的输入信号和类似的数据处理系统外围设备进行操作的锁相环，其中输入信号具有前导码部分和数据部分。 锁相环提供数字时钟信号，该数字时钟信号被锁相到前同步码部分。 这通过调整环路响应时间来实现，使得其在锁相环接收前同步码部分时开始时的幅度单调减小，并且在锁相环接收数据的至少一部分时间内继续单调减小 一部分。 响应时间可以以任何合适的方式单调减少，例如线性或指数地降低。 公开了一种与电荷泵一起使用的线性递减信号发生器的具体实施例。 还讨论了计算机模拟的结果，显示了锁定采集时间的减少和提高的抗噪声能力，缩短了前导码时间。