公开(公告)号：US08650367B2

公开(公告)日：2014-02-11

申请号：US13585268

申请日：2012-08-14

申请人： Michael S. Floyd ,  Guy L. Guthrie ,  Karthick Rajamani ,  Gregory A. Still ,  Jeffrey A. Stuecheli ,  Malcolm S. Ware

发明人： Michael S. Floyd ,  Guy L. Guthrie ,  Karthick Rajamani ,  Gregory A. Still ,  Jeffrey A. Stuecheli ,  Malcolm S. Ware

IPC分类号： G06F12/00

CPC分类号： G06Q50/10

摘要： An apparatus for providing system memory usage throttling within a data processing system having multiple chiplets is disclosed. The apparatus includes a system memory, a memory access collection module, a memory credit accounting module and a memory throttle counter. The memory access collection module receives a first set of signals from a first cache memory within a chiplet and a second set of signals from a second cache memory within the chiplet. The memory credit accounting module tracks the usage of the system memory on a per user virtual partition basis according to the results of cache accesses extracted from the first and second set of signals from the first and second cache memories within the chiplet. The memory throttle counter for provides a throttle control signal to prevent any access to the system memory when the system memory usage has exceeded a predetermined value.

公开(公告)号：US20120331231A1

公开(公告)日：2012-12-27

申请号：US13585268

申请日：2012-08-14

申请人： Michael S. FLOYD ,  Guy L. GUTHRIE ,  Karthick RAJAMANI ,  Gregory A. STILL ,  Jeffrey A. STUECHELI ,  Malcolm S. WARE

发明人： Michael S. FLOYD ,  Guy L. GUTHRIE ,  Karthick RAJAMANI ,  Gregory A. STILL ,  Jeffrey A. STUECHELI ,  Malcolm S. WARE

IPC分类号： G06F12/08

CPC分类号： G06Q50/10

摘要： An apparatus for providing system memory usage throttling within a data processing system having multiple chiplets is disclosed. The apparatus includes a system memory, a memory access collection module, a memory credit accounting module and a memory throttle counter. The memory access collection module receives a first set of signals from a first cache memory within a chiplet and a second set of signals from a second cache memory within the chiplet. The memory credit accounting module tracks the usage of the system memory on a per user virtual partition basis according to the results of cache accesses extracted from the first and second set of signals from the first and second cache memories within the chiplet. The memory throttle counter for provides a throttle control signal to prevent any access to the system memory when the system memory usage has exceeded a predetermined value.