公开(公告)号：US4963872A

公开(公告)日：1990-10-16

申请号：US94821

申请日：1987-09-09

申请人： Georg Schneider ,  Gunter Freudig ,  Fernand Rippinger ,  Hans Braun

发明人： Georg Schneider ,  Gunter Freudig ,  Fernand Rippinger ,  Hans Braun

IPC分类号： H03K5/08 ,  H03K5/156 ,  H03M5/02

CPC分类号： H03K5/086 ,  H03K5/088 ,  H03K5/1565

摘要： An arrangement for generating mean-value-free binary signals includes a binarizing circuit which receives an analog signal to be binarized and binarizes said signal with respect to a binarizing threshold. Connected to the output of the binarizing circuit is a closed-loop control circuit which includes a differential integrator which receives at the one input the binary signal from the output of the binarizing circuit. Applied to the second input of the differential integrator is a desired value signal which corresponds to the mean value between the two signal levels of the binary signal. The differential integrator integrates the deviation between the binary signal and the desired value signal and furnishes a signal corresponding to the integrated deviation. By the signal corresponding to the integrated deviation the position of the analog signal relatively to the binarizing threshold is shifted in a sense such that the mean value of the deviation is regulated to zero. For this purpose either the signal corresponding to the integrated deviation can be superimposed on the analog signal prior to the binarizing or the binarizing threshold can be varied by the signal corresponding to the integrated deviation. Preferably, the desired value signal is produced by integration of a mean-value-free binary signal.

摘要翻译： 用于产生无平均值二进制信号的装置包括二进制化电路，其接收要二进制化的模拟信号并相对于二值化阈值对所述信号进行二值化。 连接到二值化电路的输出的是闭环控制电路，其包括差分积分器，该差分积分器在一个输入端接收来自二值化电路的输出的二进制信号。 应用于差分积分器的第二输入的是对应于二进制信号的两个信号电平之间的平均值的期望值信号。 差分积分器将二进制信号与期望值信号之间的偏差相加，并提供对应于积分偏差的信号。 通过对应于积分偏差的信号，相对于二值化阈值的模拟信号的位置在某种意义上偏移，使得偏差的平均值被调节为零。 为此，可以将对应于积分偏差的信号叠加在二值化之前的模拟信号上，或者可以通过与积分偏差相对应的信号来改变二值化阈值。 优选地，通过积分无平均值二进制信号来产生期望值信号。

公开(公告)号：US4817014A

公开(公告)日：1989-03-28

申请号：US94826

申请日：1987-09-09

申请人： Georg Schneider ,  Gunter Freudig ,  Fernand Rippinger ,  Hans Braun

发明人： Georg Schneider ,  Gunter Freudig ,  Fernand Rippinger ,  Hans Braun

IPC分类号： G06F17/15 ,  G06F15/34

CPC分类号： G06F17/15

摘要： A digital correlator for determining the offset time between two random signals offset in time with respect to each other includes an analog signal processing arrangement and a digital signal processing unit. The analog signal processing arrangement generates by binarizing and periodic sampling of the random signals and their derivatives binary signals, each of which represents the polarity of one of the random signals or the derivative of a random signal at the sampling instants. The digital signal processing unit includes two delay circuits, each of which imparts to one of the binary signals a delay of an adjustable multiple of the sampling period. Each delay circuit is formed by a write-read memory into the memory cells of which the consecutive bits of the binary signal to be delayed are written at the sampling rate under consecutive write memory addresses and out of the memory cells of which the stored bits are read at the sampling rate under consecutive read memory addresses differing from the write memory addresses by an adjustable address difference. Furthermore, the digital signal processing unit comprises two correlation units, each of which receives a delayed binary signal, an undelayed binary signal and a derivative binary signal corresponding to the derivative of the undelayed binary signal. Each correlation unit counts the sampling periods which are contained in an averaging time interval and in which a quantity calculated from the binary signals supplied assumes a positive numerical value or a negative numerical value. A computing and control circuit calculates from the two counts estimated values of correlation coefficients and their derivatives and controls the adjustable address difference in each delay circuit in dependence upon said estimated values so that the delay time is kept equal to the offset time.

摘要翻译： 用于确定相对于彼此在时间上偏移的两个随机信号之间的偏移时间的数字相关器包括模拟信号处理装置和数字信号处理单元。 模拟信号处理装置通过对随机信号及其导数二进制信号进行二值化和周期性采样生成二进制信号，每个二进制信号表示随机信号之一的极性或取样时刻的随机信号的导数。 数字信号处理单元包括两个延迟电路，每个延迟电路使二进制信号之一赋予采样周期的可调整倍数的延迟。 每个延迟电路由写入存储器形成到存储单元中，在其存储单元中，要延迟的二进制信号的连续位以连续写入存储器地址的采样率被写入，并且存储单元中存储的位为 在与存储器地址不同的连续读取存储器地址下以可调节的地址差读取采样率。 此外，数字信号处理单元包括两个相关单元，每个相关单元接收对应于未延迟二进制信号的导数的延迟二进制信号，未延迟二进制信号和导数二进制信号。 每个相关单元对包含在平均时间间隔中的采样周期进行计数，其中从所提供的二进制信号计算出的数量为正数值或负数值。 计算和控制电路根据相关系数的两个计数估计值及其导数来计算，并且根据所述估计值控制每个延迟电路中的可调地址差，使得延迟时间保持等于偏移时间。