ARITHMETIC METHOD AND APPARATUS FOR SUPPORTING AES AND ARIA ENCRYPTION/DECRYPTION FUNCTIONS
    1.
    发明申请
    ARITHMETIC METHOD AND APPARATUS FOR SUPPORTING AES AND ARIA ENCRYPTION/DECRYPTION FUNCTIONS 审中-公开
    用于支持AES和ARIA加密/分解函数的算法和装置

    公开(公告)号:US20120076294A1

    公开(公告)日:2012-03-29

    申请号:US13311683

    申请日:2011-12-06

    CPC classification number: H04L9/0631 H04L2209/122

    Abstract: Provided are an arithmetic method and apparatus for supporting Advanced Encryption Standard (AES) and Academy, Research Institute and Agency (ARIA) encryption/decryption functions. The apparatus includes: a key scheduler for generating a round key using an input key; and a round function calculator for generating encrypted/decrypted data using input data and the round key. Here, the round function calculator includes an integrated substitution layer and an integrated diffusion layer capable of performing both AES and ARIA algorithms.

    Abstract translation: 提供了用于支持高级加密标准(AES)和Academy,Research Institute and Agency(ARIA)加密/解密功能的算术方法和装置。 该装置包括:密钥调度器,用于使用输入密钥生成圆键; 以及循环函数计算器,用于使用输入数据和所述循环密钥来生成加密/解密数据。 这里,循环函数计算器包括集成替代层和能够执行AES和ARIA算法的集成扩散层。

    Arithmetic method and apparatus for supporting AES and ARIA encryption/decryption functions
    2.
    发明授权
    Arithmetic method and apparatus for supporting AES and ARIA encryption/decryption functions 有权
    用于支持AES和ARIA加密/解密功能的算术方法和装置

    公开(公告)号:US08094815B2

    公开(公告)日:2012-01-10

    申请号:US11923806

    申请日:2007-10-25

    CPC classification number: H04L9/0631 H04L2209/122

    Abstract: Provided are an arithmetic method and apparatus for supporting Advanced Encryption Standard (AES) and Academy, Research Institute and Agency (ARIA) encryption/decryption functions. The apparatus includes: a key scheduler for generating a round key using an input key; and a round function calculator for generating encrypted/decrypted data using input data and the round key. Here, the round function calculator includes an integrated substitution layer and an integrated diffusion layer capable of performing both AES and ARIA algorithms.

    Abstract translation: 提供了用于支持高级加密标准(AES)和Academy,Research Institute and Agency(ARIA)加密/解密功能的算术方法和装置。 该装置包括:密钥调度器,用于使用输入密钥生成圆键; 以及循环函数计算器,用于使用输入数据和所述循环密钥来生成加密/解密数据。 这里,循环函数计算器包括集成替代层和能够执行AES和ARIA算法的集成扩散层。

    ARITHMETIC METHOD AND APPARATUS FOR SUPPORTING AES AND ARIA ENCRYPTION/DECRYPTION FUNCTIONS
    3.
    发明申请
    ARITHMETIC METHOD AND APPARATUS FOR SUPPORTING AES AND ARIA ENCRYPTION/DECRYPTION FUNCTIONS 有权
    用于支持AES和ARIA加密/分解函数的算法和装置

    公开(公告)号:US20080112560A1

    公开(公告)日:2008-05-15

    申请号:US11923806

    申请日:2007-10-25

    CPC classification number: H04L9/0631 H04L2209/122

    Abstract: Provided are an arithmetic method and apparatus for supporting Advanced Encryption Standard (AES) and Academy, Research Institute and Agency (ARIA) encryption/decryption functions. The apparatus includes: a key scheduler for generating a round key using an input key; and a round function calculator for generating encrypted/decrypted data using input data and the round key. Here, the round function calculator includes an integrated substitution layer and an integrated diffusion layer capable of performing both AES and ARIA algorithms.

    Abstract translation: 提供了用于支持高级加密标准(AES)和Academy,Research Institute and Agency(ARIA)加密/解密功能的算术方法和装置。 该装置包括:密钥调度器,用于使用输入密钥生成圆键; 以及循环函数计算器,用于使用输入数据和所述循环密钥来生成加密/解密数据。 这里,循环函数计算器包括集成替代层和能够执行AES和ARIA算法的集成扩散层。

    APPARATUS FOR COMPUTING STREAMCIPHER TSC-4
    4.
    发明申请
    APPARATUS FOR COMPUTING STREAMCIPHER TSC-4 有权
    计算流式细胞仪TSC-4的装置

    公开(公告)号:US20090147946A1

    公开(公告)日:2009-06-11

    申请号:US12269954

    申请日:2008-11-13

    CPC classification number: H04L9/065 H04L2209/122

    Abstract: Provided is an apparatus for computing a T-function based Stream Cipher (TSC)-4 stream cipher. The apparatus includes: two T-function units; and a nonlinear filter for receiving bits output from the two T-function units and generating an 8-bit output sequence per clock. Each of the T-function units includes: a first register for storing an internal state value of the lower N bits; an N-bit internal state updater for updating the internal state value of the lower N-bits stored in the first register; an intermediate result register for storing an intermediate result value output from the N-bit internal state updater; a second register for storing an internal state value of the upper M bits; and an M-bit internal state updater for updating the internal state value of the upper M bits stored in the second register using the value stored in the intermediate result register.

    Abstract translation: 提供了一种用于计算基于T函数的流密码(TSC)-4流密码的装置。 该装置包括:两个T功能单元; 以及用于接收从两个T功能单元输出的位并且每个时钟产生8位输出序列的非线性滤波器。 每个T功能单元包括:第一寄存器,用于存储低N位的内部状态值; N位内部状态更新器,用于更新存储在第一寄存器中的较低N位的内部状态值; 中间结果寄存器,用于存储从N位内部状态更新器输出的中间结果值; 第二寄存器,用于存储高位M位的内部状态值; 以及M位内部状态更新器,用于使用存储在中间结果寄存器中的值来更新存储在第二寄存器中的上位M位的内部状态值。

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