公开(公告)号：US20110231463A1

公开(公告)日：2011-09-22

申请号：US12724510

申请日：2010-03-16

Applicant: Manoj Gunwani ,  Harekrishna Verma

Inventor： Manoj Gunwani ,  Harekrishna Verma

IPC: G06F17/10

CPC classification number: H03K19/177

Abstract: A Signal Processing Engine (SPE) includes circuitry for generating a selectable forward tap and a selectable reverse tap from a forward delay chain and a reverse delay chain, respectively. An add/subtract unit arithmetically combines the selectable forward tap and the selectable reverse tap to generate an intermediate output. A multiplier combines the intermediate output and a coefficient output from a circular coefficient buffer to generate a multiply result. Another adder/subtractor combines the multiply result with a second term including a processed input or an accumulator feedback by bypassing, adding, or subtracting the second term with the multiply result to generate an accumulator output. The accumulator output may be delayed a programmable number of clock cycles to generate a processed output. In some embodiments, the SPE is coupled to programmable logic blocks forming a programmable logic array through a programmable SPE routing block.

Abstract translation: 信号处理引擎（SPE）包括用于分别从前向延迟链和反向延迟链产生可选择的前向抽头和可选择反向抽头的电路。 加法/减法单元将可选择的正向抽头和可选择的反向抽头算术组合以产生中间输出。 乘法器将中间输出和来自圆形系数缓冲器的系数输出相结合以产生乘法结果。 另一个加法器/减法器将乘法结果与包括经处理的输入或累加器反馈的第二项组合，通过使用乘法结果旁路，相加或减去第二项以产生累加器输出。 累加器输出可以延迟可编程的时钟周期数以产生经处理的输出。 在一些实施例中，SPE通过可编程SPE路由块耦合到形成可编程逻辑阵列的可编程逻辑块。

公开(公告)号：US20110225222A1

公开(公告)日：2011-09-15

申请号：US12724302

申请日：2010-03-15

Applicant: Manoj Gunwani ,  Harekrishna Verma

Inventor： Manoj Gunwani ,  Harekrishna Verma

IPC: G06F17/16 ,  G06F5/01

CPC classification number: G06F7/5446

Abstract: A CORDIC engine includes an N-stage CORDIC processor for performing N micro-iterations of a CORDIC algorithm and generating a 3-vector CORDIC output responsive to a 3-vector CORDIC input. A counter counts a number of M macro-iterations for the CORDIC algorithm and indicates a start of the cycle iterations. A multiplexer selects an input to the N-stage CORDIC processor as the 3-vector CORDIC input at the start of the cycle iterations or the 3-vector CORDIC output at other times. The CORDIC algorithm is complete after N*M clock cycles by generating N micro-iterations for each of the M macro-iterations. In some embodiments, the CORDIC engine is coupled to programmable logic blocks as part of a programmable logic array.

Abstract translation: CORDIC引擎包括N级CORDIC处理器，用于执行CORDIC算法的N个微迭代，并响应于3向量CORDIC输入生成3向量CORDIC输出。 一个计数器计数CORDIC算法的M个宏迭代次数，并指示周期迭代的开始。 复用器在循环迭代开始时将N级CORDIC处理器的输入选择为3向量CORDIC输入，或者在其他时间选择3向量CORDIC输出。 CORDIC算法在N * M个时钟周期之后通过为M个宏迭代中的每一个生成N个微迭代来完成。 在一些实施例中，作为可编程逻辑阵列的一部分，CORDIC引擎耦合到可编程逻辑块。

公开(公告)号：US08612503B2

公开(公告)日：2013-12-17

申请号：US12724510

申请日：2010-03-16

Applicant: Manoj Gunwani ,  Harekrishna Verma

Inventor： Manoj Gunwani ,  Harekrishna Verma

IPC: G06F17/10

CPC classification number: H03K19/177

Abstract: A Signal Processing Engine (SPE) includes circuitry for generating a selectable forward tap and a selectable reverse tap from a forward delay chain and a reverse delay chain, respectively. An add/subtract unit arithmetically combines the selectable forward tap and the selectable reverse tap to generate an intermediate output. A multiplier combines the intermediate output and a coefficient output from a circular coefficient buffer to generate a multiply result. Another adder/subtractor combines the multiply result with a second term including a processed input or an accumulator feedback by bypassing, adding, or subtracting the second term with the multiply result to generate an accumulator output. The accumulator output may be delayed a programmable number of clock cycles to generate a processed output. In some embodiments, the SPE is coupled to programmable logic blocks forming a programmable logic array through a programmable SPE routing block.

Abstract translation: 信号处理引擎（SPE）包括用于分别从前向延迟链和反向延迟链产生可选择的前向抽头和可选择反向抽头的电路。 加法/减法单元将可选择的正向抽头和可选择的反向抽头算术组合以产生中间输出。 乘法器将中间输出和来自圆形系数缓冲器的系数输出相结合以产生乘法结果。 另一个加法器/减法器将乘法结果与包括经处理的输入或累加器反馈的第二项组合，通过使用乘法结果旁路，相加或减去第二项以产生累加器输出。 累加器输出可以延迟可编程的时钟周期数以产生经处理的输出。 在一些实施例中，SPE通过可编程SPE路由块耦合到形成可编程逻辑阵列的可编程逻辑块。

公开(公告)号：US08572151B2

公开(公告)日：2013-10-29

申请号：US12724302

申请日：2010-03-15

Applicant: Manoj Gunwani ,  Harekrishna Verma

Inventor： Manoj Gunwani ,  Harekrishna Verma

IPC: G06F7/38

CPC classification number: G06F7/5446

Abstract: A CORDIC engine includes an N-stage CORDIC processor for performing N micro-iterations of a CORDIC algorithm and generating a 3-vector CORDIC output responsive to a 3-vector CORDIC input. A counter counts a number of M macro-iterations for the CORDIC algorithm and indicates a start of the cycle iterations. A multiplexer selects an input to the N-stage CORDIC processor as the 3-vector CORDIC input at the start of the cycle iterations or the 3-vector CORDIC output at other times. The CORDIC algorithm is complete after N*M clock cycles by generating N micro-iterations for each of the M macro-iterations. In some embodiments, the CORDIC engine is coupled to programmable logic blocks as part of a programmable logic array.

Abstract translation: CORDIC引擎包括N级CORDIC处理器，用于执行CORDIC算法的N个微迭代，并响应于3向量CORDIC输入生成3向量CORDIC输出。 一个计数器计数CORDIC算法的M个宏迭代次数，并指示周期迭代的开始。 复用器在循环迭代开始时将N级CORDIC处理器的输入选择为3向量CORDIC输入，或者在其他时间选择3向量CORDIC输出。 CORDIC算法在N * M个时钟周期之后通过为M个宏迭代中的每一个生成N个微迭代来完成。 在一些实施例中，作为可编程逻辑阵列的一部分，CORDIC引擎耦合到可编程逻辑块。