公开(公告)号：US20070203662A1

公开(公告)日：2007-08-30

申请号：US11474393

申请日：2006-06-26

申请人： Hidetoshi Sugiyama ,  Masao Nakajima ,  Haruyuki Mouri ,  Hideaki Suzuki

发明人： Hidetoshi Sugiyama ,  Masao Nakajima ,  Haruyuki Mouri ,  Hideaki Suzuki

IPC分类号： G06F19/00

CPC分类号： G01R31/31719 ,  G01R31/31701 ,  G01R31/31721

摘要： A testing circuit for a semiconductor device having a test mode in which the information about built-in memory cannot be read after conducting a test on a semiconductor device, and cutting a pad formed in a scribe area is provided. The scribe PAD and the scribe ROM are formed in the cutting area of a wafer. Upon power-up of a chip a, the power-on reset circuit transmits a reset signal to the mode register. After setting the initial resister value to “00”, a mode switch signal is input from the mode switch terminal, the scribe ROM is activated, and the test mode is set. In this process, a Manchester coded signal is provided from the scribe PAD, decoded by a clock of dividing frequency provided from the clock dividing circuit, the value of the register in the test mode in the mode register is set, and external reset is asserted or negated.

摘要翻译： 一种半导体器件的测试电路，具有测试模式，其中在对半导体器件进行测试之后无法读取关于内置存储器的信息，并且切割形成在划线区域中的焊盘。 划片PAD和划线ROM形成在晶片的切割区域中。 在芯片a上电时，上电复位电路将复位信号发送到模式寄存器。 将初始电阻值设置为“00”后，从模式开关端子输入模式切换信号，激活划线ROM，并设置测试模式。 在这个过程中，曼彻斯特编码信号由划片PAD提供，由时钟分频电路提供的分频时钟解码，设置模式寄存器中的测试模式中的寄存器的值，并且断言外部复位 或否定。

公开(公告)号：US07603248B2

公开(公告)日：2009-10-13

申请号：US11474393

申请日：2006-06-26

申请人： Hidetoshi Sugiyama ,  Masao Nakajima ,  Haruyuki Mouri ,  Hideaki Suzuki

发明人： Hidetoshi Sugiyama ,  Masao Nakajima ,  Haruyuki Mouri ,  Hideaki Suzuki

IPC分类号： G06F19/00

CPC分类号： G01R31/31719 ,  G01R31/31701 ,  G01R31/31721

摘要： A testing circuit for a semiconductor device having a test mode in which the information about built-in memory cannot be read after conducting a test on a semiconductor device, and cutting a pad formed in a scribe area is provided. The scribe PAD and the scribe ROM are formed in the cutting area of a wafer. Upon power-up of a chip a, the power-on reset circuit transmits a reset signal to the mode register. After setting the initial resister value to “00”, a mode switch signal is input from the mode switch terminal, the scribe ROM is activated, and the test mode is set. In this process, a Manchester coded signal is provided from the scribe PAD, decoded by a clock of dividing frequency provided from the clock dividing circuit, the value of the register in the test mode in the mode register is set, and external reset is asserted or negated.

摘要翻译： 一种半导体器件的测试电路，具有测试模式，其中在对半导体器件进行测试之后无法读取关于内置存储器的信息，并且切割形成在划线区域中的焊盘。 划片PAD和划线ROM形成在晶片的切割区域中。 在芯片a上电时，上电复位电路将复位信号发送到模式寄存器。 将初始电阻值设置为“00”后，从模式开关端子输入模式切换信号，激活划线ROM，并设置测试模式。 在这个过程中，曼彻斯特编码信号由划片PAD提供，由时钟分频电路提供的分频时钟解码，设置模式寄存器中的测试模式中的寄存器的值，并且断言外部复位 或否定。