公开(公告)号：US07008848B2

公开(公告)日：2006-03-07

申请号：US10713117

申请日：2003-11-17

申请人： Woon-kyung Lee ,  He-jueng Lee ,  Eui-do Kim

发明人： Woon-kyung Lee ,  He-jueng Lee ,  Eui-do Kim

IPC分类号： H01L21/8236

CPC分类号： H01L27/112 ,  H01L27/1126

摘要： A mask read only memory (ROM) and a method of fabricating the same is provided. This mask ROM and related method is capable of reducing the pitch of buried impurity diffusion regions. In the mask ROM fabrication process, a gate insulation layer is formed over a semiconductor substrate, and parallel conductive layer patterns are formed on the gate insulation layer. These conductive layer patterns are separated from each other by a first predetermined interval and extend in the same direction. Ion implantation is then carried out using the conductive layer patterns as a mask to form buried impurity diffusion regions near the semiconductor substrate between the conductive layer patterns. A conductive layer for use in forming word lines is then formed over the entire surface of the resultant structure, and both the conductive layer and the conductive layer patterns are etched so as to form word lines and pad conductive layers. The word lines are formed to be parallel to each other, are separated from each other by a second predetermined interval, and extend in a direction perpendicular to the buried impurity diffusion regions. The pad conductive layers, which form ohmic contacts with the word lines, are formed in an island shape channel regions. These channel regions are defined as the areas between the buried impurity diffusion regions that are overlapped by the word lines.

摘要翻译： 提供了一种掩模只读存储器（ROM）及其制造方法。 该掩模ROM和相关方法能够减少掩埋的杂质扩散区的间距。 在掩模ROM制造工艺中，在半导体衬底上形成栅极绝缘层，并且在栅极绝缘层上形成平行的导电层图案。 这些导电层图案彼此分开第一预定间隔并沿相同的方向延伸。 然后使用导电层图案作为掩模进行离子注入，以在导电层图案之间的半导体衬底附近形成掩埋的杂质扩散区。 然后在所得结构的整个表面上形成用于形成字线的导电层，并且蚀刻导电层和导电层图案，以形成字线和焊盘导电层。 字线形成为彼此平行，彼此分开第二预定间隔，并且在垂直于埋置的杂质扩散区域的方向上延伸。 与字线形成欧姆接触的焊盘导电层形成为岛状沟道区域。 这些沟道区域被定义为由字线重叠的掩埋杂质扩散区域之间的区域。

公开(公告)号：US06291308B1

公开(公告)日：2001-09-18

申请号：US09372850

申请日：1999-08-12

申请人： Woon-kyung Lee ,  He-jueng Lee

发明人： Woon-kyung Lee ,  He-jueng Lee

IPC分类号： H01L2176

CPC分类号： H01L27/11293

摘要： A method for fabricating a mask ROM capable of effectively reducing the distance of buried impurity diffusion regions. The method includes stacking a pad oxide layer and a first anti-oxidation layer in sequence in a cell array region and a peripheral circuit region of a semiconductor substrate. The anti-oxidation layer is partially etched to form a first pattern defining an isolation region of the peripheral circuit region and a second pattern defining a buried impurity diffusion region of the cell array region, and a second anti-oxidation layer is stacked, and then the second anti-oxidation layer stacked in the peripheral circuit region is removed, so that the second anti-oxidation layer stacked in the cell array region remains. Then, a field oxide layer is formed in the isolation region of the peripheral circuit region, exposed by the remaining second anti-oxidation layer; and impurities are implanted to form the buried impurity diffusion region.

摘要翻译： 一种制造掩模ROM的方法，其能够有效地减少掩埋的杂质扩散区域的距离。 该方法包括在半导体衬底的单元阵列区域和外围电路区域中依次层叠衬垫氧化物层和第一抗氧化层。 部分蚀刻抗氧化层以形成限定外围电路区域的隔离区域的第一图案和限定电池阵列区域的掩埋杂质扩散区域的第二图案，并且层叠第二抗氧化层，然后 去除在周边电路区域堆叠的第二抗氧化层，从而保留堆叠在电池阵列区域中的第二抗氧化层。 然后，在外围电路区域的隔离区域中形成场氧化物层，由剩余的第二抗氧化层露出; 并且注入杂质以形成掩埋的杂质扩散区域。

公开(公告)号：US6133103A

公开(公告)日：2000-10-17

申请号：US357674

申请日：1999-07-20

申请人： He-jueng Lee ,  Ki-chang Yoon

发明人： He-jueng Lee ,  Ki-chang Yoon

IPC分类号： H01L27/112 ,  H01L21/8234 ,  H01L21/8246 ,  H01L21/8236

CPC分类号： H01L27/1126 ,  H01L21/823412

摘要： A method for fabricating a mask read only memory (ROM) is provided. A plurality of word lines functioning as a gate electrode of a cell transistor and a plurality of first anti-reflective layer patterns are sequentially formed on a semiconductor substrate. An insulator layer is formed over the entire surface of the semiconductor substrate where the plurality of first anti-reflective layer patterns and the plurality of word lines are formed. A spacer is formed at the side walls of the respective word lines by anisotropically etching the insulator layer until the plurality of word lines are exposed. A second anti-reflective layer is formed over the entire surface of the semiconductor substrate where the spacer is formed. A photoresist pattern opening the upper portion of a predetermined region of at least one word line selected among the plurality of word lines of the cell transistor to be programmed is formed on the second anti-reflective layer. An impurity is implanted into a channel region of the opened cell transistor using the photoresist pattern as an ion implantation mask.

摘要翻译： 提供了一种制造掩模只读存储器（ROM）的方法。 在半导体衬底上依次形成用作单元晶体管的栅电极的多个字线和多个第一抗反射层图案。 在形成多个第一抗反射层图案和多个字线的半导体基板的整个表面上形成绝缘体层。 通过各向异性蚀刻绝缘体层直到多个字线被暴露，在各个字线的侧壁上形成间隔物。 在半导体衬底的形成间隔物的整个表面上形成第二抗反射层。 在第二抗反射层上形成一个光刻胶图案，其打开在要编程的单元晶体管的多个字线中选择的至少一个字线的预定区域的上部。 使用光致抗蚀剂图案作为离子注入掩模将杂质注入到开孔单元晶体管的沟道区域中。