公开(公告)号：US20060026345A1

公开(公告)日：2006-02-02

申请号：US10959982

申请日：2004-10-08

申请人： Akira Nishimoto ,  Naoto Matsunami ,  Masahiko Sato ,  Hidemi Baba

发明人： Akira Nishimoto ,  Naoto Matsunami ,  Masahiko Sato ,  Hidemi Baba

IPC分类号： G06F12/08

CPC分类号： G06F11/1076 ,  G06F12/0866 ,  G06F2211/1007 ,  G06F2211/1009 ,  G06F2211/104

摘要： To correctly generate LAs even when out-of-order occurs. In a disk array system according to the present invention, a control unit includes: a host input/output unit that exchanges data and a control signal with a host connected to a disk array system; a disk input/output unit that exchanges data and a control signal with a disk; a cache memory that temporarily stores the data during transfer between the host input/output unit and the disk input/output unit in units of segments that are each formed by a plurality of blocks having a predetermined size; an MPU that controls an operation of the control unit by executing a control program; and a cache controller that controls input/output of the data into/from the cache memory, and the host input/output unit transfers, to the cache controller, transfer information containing the guarantee codes of the first blocks of the segments relating to the data transfer.

摘要翻译： 即使发生乱序，也能正确生成LAs。 在根据本发明的磁盘阵列系统中，控制单元包括：与连接到磁盘阵列系统的主机交换数据和控制信号的主机输入/输出单元; 磁盘输入/输出单元，用于与磁盘交换数据和控制信号; 高速缓存存储器，用于在主机输入/输出单元和盘输入/输出单元之间传送期间以分段为单位临时存储数据，每个段由具有预定大小的多个块形成; MPU，通过执行控制程序来控制所述控制单元的动作; 以及高速缓存控制器，其将数据输入/输出到高速缓存存储器中，并且主机输入/输出单元向高速缓存控制器传送包含与数据相关的段的第一块的保证代码的信息 转让。

公开(公告)号：US07293139B2

公开(公告)日：2007-11-06

申请号：US10959982

申请日：2004-10-08

申请人： Akira Nishimoto ,  Naoto Matsunami ,  Masahiko Sato ,  Hidemi Baba

发明人： Akira Nishimoto ,  Naoto Matsunami ,  Masahiko Sato ,  Hidemi Baba

IPC分类号： G06F12/08

CPC分类号： G06F11/1076 ,  G06F12/0866 ,  G06F2211/1007 ,  G06F2211/1009 ,  G06F2211/104

摘要： To correctly generate LAs even when out-of-order occurs. In a disk array system according to the present invention, a control unit includes: a host input/output unit that exchanges data and a control signal with a host connected to a disk array system; a disk input/output unit that exchanges data and a control signal with a disk; a cache memory that temporarily stores the data during transfer between the host input/output unit and the disk input/output unit in units of segments that are each formed by a plurality of blocks having a predetermined size; an MPU that controls an operation of the control unit by executing a control program; and a cache controller that controls input/output of the data into/from the cache memory, and the host input/output unit transfers, to the cache controller, transfer information containing the guarantee codes of the first blocks of the segments relating to the data transfer.

摘要翻译： 即使发生乱序，也能正确生成LAs。 在根据本发明的磁盘阵列系统中，控制单元包括：与连接到磁盘阵列系统的主机交换数据和控制信号的主机输入/输出单元; 磁盘输入/输出单元，用于与磁盘交换数据和控制信号; 高速缓存存储器，用于在主机输入/输出单元和盘输入/输出单元之间传送期间以每个由具有预定尺寸的多个块形成的段为单位临时存储数据; MPU，通过执行控制程序来控制所述控制单元的动作; 以及高速缓存控制器，其将数据输入/输出到高速缓存存储器中，并且主机输入/输出单元向高速缓存控制器传送包含与数据相关的段的第一块的保证代码的信息 转让。

公开(公告)号：US5530830A

公开(公告)日：1996-06-25

申请号：US163022

申请日：1993-12-06

申请人： Hidehiko Iwasaki ,  Ryoichi Suzuki ,  Yoshinori Tsuneda ,  Katsutoshi Mizuno ,  Hidemi Baba

发明人： Hidehiko Iwasaki ,  Ryoichi Suzuki ,  Yoshinori Tsuneda ,  Katsutoshi Mizuno ,  Hidemi Baba

IPC分类号： G06F3/06 ,  G06F12/00

CPC分类号： G06F3/0601 ,  G06F2003/0692

摘要： A disk array system having a plurality of disk units includes an upper-level data transfer controller for controlling transfer of data to and from an upper-level apparatus, a data buffer for temporarily storing therein data from the upper-level apparatus, a drive data transfer controller for controlling the data transfer between the buffer and the units, and a main microprocessor for controlling the the transfer controllers. When transferring data, the microprocessor indicates an address to be used in the buffer and a distribution mode of data to the data transfer controllers so that the data transfer is conducted thereafter without intervention of the microprocessor. During the transfer, the microprocessor can generate information for a subsequent data transfer to indicate the information to the transfer controllers. After a data transfer is terminated, the pertinent transfer controller can immediately execute the next data transfer, which increases the utilization efficiency of the data bus.

摘要翻译： 具有多个盘单元的盘阵系统包括用于控制向上级装置传送数据和从上级装置传送数据的上级数据传送控制器，用于临时存储来自上级装置的数据的数据缓冲器，驱动数据 用于控制缓冲器和单元之间的数据传输的传送控制器和用于控制传送控制器的主微处理器。 当传送数据时，微处理器指示要在缓冲器中使用的地址和向数据传输控制器发送数据的分发模式，以便此后进行数据传输，而不需要微处理器的干预。 在传送过程中，微处理器可以生成用于后续数据传输的信息，以将信息指示给传送控制器。 数据传输终止后，相关的传输控制器可以立即执行下一次数据传输，从而提高数据总线的利用效率。