公开(公告)号：US20080197449A1

公开(公告)日：2008-08-21

申请号：US12035230

申请日：2008-02-21

申请人： Takayuki ARAKI ,  Junichi Shimada ,  Hirokazu Ogawa ,  Kazuhiko Fujimoto ,  Tsutomu Fujii ,  Takuya Yasui

发明人： Takayuki ARAKI ,  Junichi Shimada ,  Hirokazu Ogawa ,  Kazuhiko Fujimoto ,  Tsutomu Fujii ,  Takuya Yasui

IPC分类号： H01L23/52

CPC分类号： H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method is provided for designing a wiring structure of a wiring layer of a semiconductor integrated circuit device. The method includes a wire width detecting step of detecting a wire width of each wire in a wiring pattern of layout data, a wire identifying step of identifying a wire having a predetermined wire width or more based on a result of detection by the wire width detecting step, a wiring pitch detecting step of detecting a wiring pitch between the wire identified by the wire identifying step and another wire, and an air gap-forbidden region forming and removing step of forming or removing an air gap-forbidden region, depending on a result of detection by the wiring pitch detecting step.

摘要翻译： 提供一种用于设计半导体集成电路器件的布线层的布线结构的方法。 该方法包括：线宽检测步骤，检测布线数据的布线图案中的每条线的线宽;线识别步骤，基于线宽检测的检测结果识别具有预定线宽或更大的线的线; 步骤，检测由线识别步骤识别的线与另一线之间的布线间距的接线间距检测步骤以及形成或除去气隙禁止区域的气隙禁止区形成和移除步骤， 通过布线间距检测步骤的检测结果。