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1.发明授权Multi-link protocol reassembly assist in a parallel 1-D systolic array system 有权并行1-D收缩阵列系统中的多链路协议重组协助公开(公告)号：US07245615B1
公开(公告)日：2007-07-17
申请号：US10021714
申请日：2001-10-30
CPC分类号： H04L69/16 , H04L69/14 , H04L69/166 , H04L69/168
摘要： The present invention comprises a technique for performing a reassembly assist function that enables a processor to perform packet reassembly in a deterministic manner. The technique employed by the present invention enables a processor to reassemble a packet without having to extend its normal processing time to reassemble a varying number of fragments into a packet. The invention takes advantage of the fact that the reassembly assist can be dedicated exclusively to reassembling a packet from a series of fragments and thereby offloading the reassembly process from the processor.
摘要翻译： 本发明包括一种用于执行重组辅助功能的技术，其使得处理器能够以确定性的方式执行分组重组。 本发明采用的技术使得处理器能够重新组合分组而不必扩展其正常的处理时间，以将不同数量的片段重新组合成分组。 本发明利用了这样的事实，即重组辅助可专门用于从一系列片段重新组装分组，从而将重组过程从处理器卸载。
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公开(公告)号：US07124231B1
公开(公告)日：2006-10-17
申请号：US10172172
申请日：2002-06-14
申请人： Trevor Garner , Kenneth H. Potter , Hong-Man Wu
发明人： Trevor Garner , Kenneth H. Potter , Hong-Man Wu
IPC分类号： G06F13/36
CPC分类号： G06F13/4059
摘要： The present invention provides a technique for ordering responses received over a split transaction bus, such as a HyperTransport bus (HPT). When multiple non-posted requests are sequentially issued over the split transaction bus, control logic is used to assign each request an identifying (ID) number, e.g. up to a maximum number of outstanding requests. Similarly, each response received over the split transaction bus is assigned the same ID number as its corresponding request. Accordingly, a “response memory” comprises a unique memory block for every possible ID number, and the control logic directs a received response to its corresponding memory block. The responses are extracted from blocks of response memory in accordance with a predetermined set of ordering rules. For example, the responses may be accessed in the same order the corresponding non-posted requests were issued.
摘要翻译： 本发明提供了一种用于排序通过诸如HyperTransport总线（HPT）的分组事务总线接收的响应的技术。 当在分割事务总线上顺序地发出多个非发布请求时，使用控制逻辑来分配每个请求，例如识别（ID）号码。 达到最大数量的未完成请求。 类似地，通过分割事务总线接收的每个响应被分配与其相应请求相同的ID号。 因此，“响应存储器”包括用于每个可能的ID号的唯一的存储块，并且控制逻辑将接收的响应引导到其对应的存储块。 根据预定的排序规则集从响应存储器块中提取响应。 例如，可以按相同的顺序访问相应的未发布的请求。
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3.发明授权Technique for nondisruptively recovering from a processor failure in a multi-processor flow device 有权在多处理器流量设备中从处理器故障中中恢复的技术公开(公告)号：US07324438B1
公开(公告)日：2008-01-29
申请号：US10365973
申请日：2003-02-13
CPC分类号： H04L43/0817 , H04L41/0631 , H04L41/0654
摘要： A technique non-disruptively recovers from a processor failure in a multi-processor flow device, such as an intermediate network node of a computer network. Data relating to a particular data flow of a processor within the node is tagged with specific information used to detect and recover from a failure of the processor without affecting data from other processors of the node. A data path management device tags the data with the specific information reflecting the processor issuing the data and a state of the processor. When the tagged data subsequently passes through the data path management device, the specific information is compared with current information for the issuing processor. If the comparison indicates that the specific information is valid, the data path management device forwards the related data flow through the node. If the comparison indicates that the specific information is invalid, the data and its related data flow are discarded and “cleanly” purged from the node.
摘要翻译： 一种技术在诸如计算机网络的中间网络节点的多处理器流设备中从处理器故障中不间断地恢复。 与节点内的处理器的特定数据流有关的数据被标记有用于检测和恢复处理器的故障的特定信息，而不影响来自节点的其他处理器的数据。 数据路径管理装置使用反映处理器发出数据的特定信息和处理器的状态来标记数据。 当标签数据随后通过数据路径管理装置时，将特定信息与发布处理器的当前信息进行比较。 如果比较表明特定信息有效，则数据路径管理设备通过节点转发相关数据流。 如果比较表明特定信息无效，则数据及其相关数据流被丢弃，并从节点“清除”清除。
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4.发明授权Scheduling assist for data networking packet dequeuing in a parallel 1-D systolic array system 有权并行1-D收缩阵列系统中的数据网络包排队的调度辅助公开(公告)号：US07085229B1
公开(公告)日：2006-08-01
申请号：US10032844
申请日：2001-10-24
CPC分类号： H04L49/901 , H04L47/2433 , H04L47/50
摘要： The present invention comprises a scheduling assist function (scheduling assist) that enables a processor to schedule events and be notified when these events expire. In addition, the present invention includes features that enable a processor to associate these events with output channels and enable the processor to quickly locate output channels (links) that are available and ready to be serviced. The invention takes advantage of the fact that the scheduling assist can be dedicated exclusively to scanning tables in its own dedicated memories looking for events that have expired and/or output channels that are available and not involve the processor in the search for output channels that are available and ready to be serviced.
摘要翻译： 本发明包括调度辅助功能（调度辅助），其使得处理器能够调度事件并且当这些事件到期时被通知。 此外，本发明还包括能够使处理器将这些事件与输出通道相关联的功能，并使得处理器能够快速地定位可用且准备待维护的输出通道（链接）。 本发明利用这样的事实，即调度辅助专用于专用于在其自己的专用存储器中扫描表，其中查找具有到期的事件和/或可用的输出通道，并且不涉及处理器搜索输出通道 可用并准备服务。
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