Inverter apparatus with built-in programmable logic-controller
    1.
    发明申请
    Inverter apparatus with built-in programmable logic-controller 审中-公开
    具有内置可编程逻辑控制器的变频器

    公开(公告)号:US20070013357A1

    公开(公告)日:2007-01-18

    申请号:US11178328

    申请日:2005-07-12

    IPC分类号: B23K11/24

    CPC分类号: G05B19/05 G05B2219/15124

    摘要: An inverter apparatus is incorporated with a built-in programmable logic-controller (PLC). The PLC includes internal memory for directly outputting control signal to provide inverter operation control without time delay and noise. The inverter apparatus includes external terminals for function assignment and an external program can be coded for expanding the function of the inverter apparatus through the external terminals. The inverter apparatus of the present invention can overcome the problems of limited function and complicated wiring.

    摘要翻译: 逆变器装置内置有可编程逻辑控制器(PLC)。 PLC包括用于直接输出控制信号的内部存储器,以提供无延迟和噪声的变频器运行控制。 逆变器装置包括用于功能分配的外部端子,并且可以对外部程序进行编码,以通过外部端子来扩展逆变器装置的功能。 本发明的逆变器装置可以克服功能有限和布线复杂的问题。

    DUAL CPU INVERTER SYSTEM AND METHOD FOR THE SAME
    2.
    发明申请
    DUAL CPU INVERTER SYSTEM AND METHOD FOR THE SAME 审中-公开
    双CPU逆变器系统及其相关方法

    公开(公告)号:US20080201569A1

    公开(公告)日:2008-08-21

    申请号:US11677137

    申请日:2007-02-21

    IPC分类号: G06F9/00

    CPC分类号: H02M7/48 H02M2001/0012

    摘要: A dual CPU inverter system includes a power module and a control module electrically connected to each other and each having a CPU, a RAM and a ROM. After power on, the two modules can read the respective ROM data to the respective RAM to speed up the ready state. When external IO intends to store command parameters, the dual CPU inverter system can judge which module is the destination for the command parameter and send the command parameter to the ROM respectively. Therefore, the communication load between the two modules can be reduced.

    摘要翻译: 双CPU逆变器系统包括彼此电连接并且具有CPU,RAM和ROM的电源模块和控制模块。 上电后,两个模块可以将相应的ROM数据读取到相应的RAM,以加速就绪状态。 当外部IO意图存储命令参数时,双CPU变频器系统可以判断哪个模块是命令参数的目的地,并将命令参数分别发送到ROM。 因此,可以减少两个模块之间的通信负载。