公开(公告)号：US20070029575A1

公开(公告)日：2007-02-08

申请号：US11195633

申请日：2005-08-03

申请人： Hao Zhang ,  Yuan-Wei Zheng ,  Hui-Fang Hsu ,  Juan-Li Liu

发明人： Hao Zhang ,  Yuan-Wei Zheng ,  Hui-Fang Hsu ,  Juan-Li Liu

IPC分类号： H01L27/10 ,  H01L21/82

CPC分类号： H01L27/112

摘要： The structure and method of measuring the capacitance comprising a first buried doped area and a heavily doped area in a semiconductor substrate. The heavily doped area is parallel to the buried doped area. Several second buried doped areas, the first oxide layers and the second oxide layers are formed in the semiconductor substrate. Any of the second buried doped areas is perpendicular to the first buried doped area. One end of the second buried doped area is connected to the first buried doped area, and another end is connected to the heavily doped area. Any of the first oxide layers is overlaid on the second buried doped area. Any of the second oxide layers is placed between any two first oxide layers, and the thickness of the second oxide layer is thinner than the thickness of the first oxide layer. At least two first and several second polysilicon rows are formed on the semiconductor substrate, and wherein two first polysilicon rows are respectively placed on two sides of the second buried doped areas. Any of the second polysilicon rows is perpendicular to the first polysilicon row therein. One end of each of the second polysilicon rows is not connected to two fist polysilicon rows. The structure of the present invention is applied to obtain the individual capacitance in relation to the word line.

摘要翻译： 测量电容的结构和方法包括半导体衬底中的第一掩埋掺杂区域和重掺杂区域。 重掺杂区域平行于埋入掺杂区域。 几个第二掩埋掺杂区域，第一氧化物层和第二氧化物层形成在半导体衬底中。 第二掩埋掺杂区域中的任一个垂直于第一掩埋掺杂区域。 第二掩埋掺杂区域的一端连接到第一掩埋掺杂区域，另一端连接到重掺杂区域。 任何第一氧化物层被覆盖在第二掩埋掺杂区域上。 任何第二氧化物层被放置在任何两个第一氧化物层之间，并且第二氧化物层的厚度比第一氧化物层的厚度薄。 在半导体衬底上形成至少两个第一和多个第二多晶硅行，并且其中两个第一多晶硅行分别放置在第二掩埋掺杂区的两侧。 任何第二多晶硅行垂直于其中的第一多晶硅行。 每个第二多晶硅行的一端不连接到两个第一多晶硅行。 应用本发明的结构来获得相对于字线的单独电容。