公开(公告)号：US20070025644A1

公开(公告)日：2007-02-01

申请号：US11191762

申请日：2005-07-28

Applicant: Ghy-Bin Wang ,  Ming-Sung Huang ,  Inn Liu

Inventor： Ghy-Bin Wang ,  Ming-Sung Huang ,  Inn Liu

IPC: G06K9/32

CPC classification number: G06T3/4007

Abstract: A graphics display adapter has a row interpolator circuit connected to receive the source pixel data synchronized at a first clock rate and to interpolate groups of pixels of row at a second clock rate. A row interpolated storage device receives and retains interpolated source pixel data of each row at the second clock rate. A column interpolator circuit extracts the interpolated source pixel data at a third clock rate. The column interpolator circuit then interpolates groupings of the interpolated source pixel data at the third clock rate and transmits the destination graphic pixel data for display. The second clock rate maybe equal to the first clock rate or the faster of the first and third clock rates.

Abstract translation: 图形显示适配器具有连接用于接收以第一时钟速率同步的源像素数据并以第二时钟速率内插行的像素组的行内插器电路。 行内插存储装置以第二时钟速率接收并保持每行的内插源像素数据。 列插值器电路以第三时钟速率提取内插源像素数据。 然后，列插值器电路以第三时钟速率内插内插源像素数据的分组，并发送用于显示的目的地图形像素数据。 第二个时钟速率可能等于第一个时钟速率或第一个和第三个时钟速率的速度。