公开(公告)号：US20070045827A1

公开(公告)日：2007-03-01

申请号：US11508176

申请日：2006-08-23

申请人： Sang-jib Han ,  Jai-kyeong Shinn

发明人： Sang-jib Han ,  Jai-kyeong Shinn

IPC分类号： H01L23/34

CPC分类号： G11C5/04 ,  H01L23/49575 ,  H01L23/50 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/48247 ,  H01L2224/4826 ,  H01L2224/48465 ,  H01L2224/49113 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A semiconductor multi-chip package includes: a first semiconductor memory chip having n address pads, a first control pad, and a first address controller; and a second semiconductor memory chip whose memory density is greater, e.g., at least 1.5 times greater, than the first semiconductor memory chip and which is disposed on the first semiconductor memory chip, and has (n+1) address pads, a second control pad, and a second address controller. The n address pads of the first semiconductor memory chip and the n address pads of the second semiconductor memory chip are respectively connected to corresponding n address pins. The first and second control pads are connected to a control pin. The first and second address controllers are operable in a mutually exclusive manner, e.g., manner of activation, according to a signal applied to the control pin.

摘要翻译： 一种半导体多芯片封装，包括：具有n个地址焊盘的第一半导体存储器芯片，第一控制焊盘和第一地址控制器; 以及第二半导体存储器芯片，其存储密度比第一半导体存储器芯片大，比第一半导体存储器芯片大至少1.5倍，并且设置在第一半导体存储器芯片上，并且具有（n + 1）个地址焊盘，第二控制 垫和第二地址控制器。 第一半导体存储器芯片的n个地址焊盘和第二半导体存储器芯片的n个地址焊盘分别连接到相应的n个地址引脚。 第一和第二控制焊盘连接到控制引脚。 根据施加到控制引脚的信号，第一和第二地址控制器可以互相排斥的方式操作，例如激活的方式。

公开(公告)号：US07486532B2

公开(公告)日：2009-02-03

申请号：US11508176

申请日：2006-08-23

申请人： Sang-jib Han ,  Jai-kyeong Shinn

发明人： Sang-jib Han ,  Jai-kyeong Shinn

IPC分类号： G11C5/02

CPC分类号： G11C5/04 ,  H01L23/49575 ,  H01L23/50 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/48247 ,  H01L2224/4826 ,  H01L2224/48465 ,  H01L2224/49113 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A semiconductor multi-chip package includes: a first semiconductor memory chip having n address pads, a first control pad, and a first address controller; and a second semiconductor memory chip whose memory density is greater, e.g., at least 1.5 times greater, than the first semiconductor memory chip and which is disposed on the first semiconductor memory chip, and has (n+1) address pads, a second control pad, and a second address controller. The n address pads of the first semiconductor memory chip and the n address pads of the second semiconductor memory chip are respectively connected to corresponding n address pins. The first and second control pads are connected to a control pin. The first and second address controllers are operable in a mutually exclusive manner, e.g., manner of activation, according to a signal applied to the control pin.

摘要翻译： 一种半导体多芯片封装，包括：具有n个地址焊盘的第一半导体存储器芯片，第一控制焊盘和第一地址控制器; 以及第二半导体存储器芯片，其存储密度比第一半导体存储器芯片大，比第一半导体存储器芯片大至少1.5倍，并且设置在第一半导体存储器芯片上，并且具有（n + 1）个地址焊盘，第二控制 垫和第二地址控制器。 第一半导体存储器芯片的n个地址焊盘和第二半导体存储器芯片的n个地址焊盘分别连接到相应的n个地址引脚。 第一和第二控制焊盘连接到控制引脚。 根据施加到控制引脚的信号，第一和第二地址控制器可以互相排斥的方式操作，例如激活的方式。